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radv: Remove first_task and ib_addr/ib_stride.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22139>
This commit is contained in:
Timur Kristóf
Marge Bot
parent
945384b504
commit
8a426be553
6 changed files with 22 additions and 115 deletions
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@ -7896,9 +7896,8 @@ radv_cs_emit_indirect_mesh_draw_packet(struct radv_cmd_buffer *cmd_buffer, uint3
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cmd_buffer->state.last_drawid = -1;
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cmd_buffer->state.last_vertex_offset = -1;
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/* Note: firstTask/firstVertex is not supported by this draw packet. */
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uint32_t xyz_dim_reg = (base_reg + 4 - SI_SH_REG_OFFSET) >> 2;
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uint32_t draw_id_reg = (base_reg + 16 - SI_SH_REG_OFFSET) >> 2;
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uint32_t xyz_dim_reg = (base_reg - SI_SH_REG_OFFSET) >> 2;
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uint32_t draw_id_reg = (base_reg + 12 - SI_SH_REG_OFFSET) >> 2;
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uint32_t draw_id_enable = !!cmd_buffer->state.graphics_pipeline->uses_drawid;
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uint32_t xyz_dim_enable = 1; /* TODO: disable XYZ_DIM when unneeded */
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@ -8014,7 +8013,7 @@ radv_cs_emit_dispatch_taskmesh_gfx_packet(struct radv_cmd_buffer *cmd_buffer)
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assert(ring_entry_loc->sgpr_idx != -1);
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uint32_t base_reg = cmd_buffer->state.graphics_pipeline->vtx_base_sgpr;
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uint32_t xyz_dim_reg = ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2;
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uint32_t xyz_dim_reg = (base_reg - SI_SH_REG_OFFSET) >> 2;
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uint32_t ring_entry_reg = ((base_reg + ring_entry_loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2;
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uint32_t xyz_dim_en = 1; /* TODO: disable XYZ_DIM when unneeded */
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uint32_t mode1_en = 1; /* legacy fast launch mode */
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@ -8080,15 +8079,13 @@ radv_emit_userdata_vertex_drawid(struct radv_cmd_buffer *cmd_buffer, uint32_t ve
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ALWAYS_INLINE static void
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radv_emit_userdata_mesh(struct radv_cmd_buffer *cmd_buffer,
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const uint32_t x, const uint32_t y, const uint32_t z,
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const uint32_t first_task)
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const uint32_t x, const uint32_t y, const uint32_t z)
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{
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struct radv_cmd_state *state = &cmd_buffer->state;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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const bool uses_drawid = state->graphics_pipeline->uses_drawid;
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radeon_set_sh_reg_seq(cs, state->graphics_pipeline->vtx_base_sgpr, state->graphics_pipeline->vtx_emit_num);
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radeon_emit(cs, first_task);
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radeon_emit(cs, x);
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radeon_emit(cs, y);
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radeon_emit(cs, z);
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@ -8100,45 +8097,22 @@ radv_emit_userdata_mesh(struct radv_cmd_buffer *cmd_buffer,
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}
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ALWAYS_INLINE static void
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radv_emit_userdata_mesh_first_task_0_draw_id_0(struct radv_cmd_buffer *cmd_buffer)
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radv_emit_userdata_mesh_draw_id_0(struct radv_cmd_buffer *cmd_buffer)
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{
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struct radv_cmd_state *state = &cmd_buffer->state;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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struct radv_graphics_pipeline *pipeline = state->graphics_pipeline;
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const bool uses_drawid = pipeline->uses_drawid;
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radeon_set_sh_reg_seq(cs, pipeline->vtx_base_sgpr, 1);
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radeon_emit(cs, 0);
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if (uses_drawid) {
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radeon_set_sh_reg_seq(cs, pipeline->vtx_base_sgpr + (pipeline->vtx_emit_num - 1) * 4, 1);
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radeon_emit(cs, 0);
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}
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}
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ALWAYS_INLINE static void
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radv_emit_userdata_task_ib_only(struct radv_cmd_buffer *cmd_buffer, uint64_t ib_va,
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uint32_t ib_stride)
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{
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struct radv_shader *task_shader = cmd_buffer->state.shaders[MESA_SHADER_TASK];
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struct radeon_cmdbuf *cs = cmd_buffer->ace_internal.cs;
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const struct radv_userdata_info *task_ib_loc = radv_get_user_sgpr(task_shader, AC_UD_CS_TASK_IB);
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if (task_ib_loc->sgpr_idx != -1) {
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assert(task_ib_loc->num_sgprs == 3);
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unsigned task_ib_reg = R_00B900_COMPUTE_USER_DATA_0 + task_ib_loc->sgpr_idx * 4;
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radeon_set_sh_reg_seq(cs, task_ib_reg, 3);
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radeon_emit(cs, ib_va);
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radeon_emit(cs, ib_va >> 32);
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radeon_emit(cs, ib_stride);
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}
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}
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ALWAYS_INLINE static void
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radv_emit_userdata_task(struct radv_cmd_buffer *cmd_buffer, uint32_t x, uint32_t y, uint32_t z,
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uint32_t draw_id, uint32_t first_task, uint64_t ib_va)
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uint32_t draw_id)
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{
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struct radv_shader *task_shader = cmd_buffer->state.shaders[MESA_SHADER_TASK];
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struct radeon_cmdbuf *cs = cmd_buffer->ace_internal.cs;
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@ -8164,8 +8138,6 @@ radv_emit_userdata_task(struct radv_cmd_buffer *cmd_buffer, uint32_t x, uint32_t
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radeon_set_sh_reg_seq(cs, draw_id_reg, 1);
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radeon_emit(cs, draw_id);
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}
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radv_emit_userdata_task_ib_only(cmd_buffer, ib_va, first_task ? 8 : 0);
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}
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/* Bind an internal index buffer for GPUs that hang with 0-sized index buffers to handle robustness2
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@ -8361,13 +8333,12 @@ radv_emit_direct_draw_packets(struct radv_cmd_buffer *cmd_buffer, const struct r
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ALWAYS_INLINE static void
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radv_emit_direct_mesh_draw_packet(struct radv_cmd_buffer *cmd_buffer,
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uint32_t x, uint32_t y, uint32_t z,
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uint32_t first_task)
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uint32_t x, uint32_t y, uint32_t z)
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{
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const uint32_t view_mask = cmd_buffer->state.render.view_mask;
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const uint32_t count = x * y * z;
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radv_emit_userdata_mesh(cmd_buffer, x, y, z, first_task);
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radv_emit_userdata_mesh(cmd_buffer, x, y, z);
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if (!view_mask) {
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radv_cs_emit_draw_packet(cmd_buffer, count, 0);
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@ -8404,7 +8375,7 @@ radv_emit_indirect_mesh_draw_packets(struct radv_cmd_buffer *cmd_buffer,
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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radv_emit_userdata_mesh_first_task_0_draw_id_0(cmd_buffer);
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radv_emit_userdata_mesh_draw_id_0(cmd_buffer);
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if (!state->render.view_mask) {
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radv_cs_emit_indirect_mesh_draw_packet(cmd_buffer, info->count, count_va, info->stride);
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@ -8418,23 +8389,14 @@ radv_emit_indirect_mesh_draw_packets(struct radv_cmd_buffer *cmd_buffer,
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ALWAYS_INLINE static void
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radv_emit_direct_taskmesh_draw_packets(struct radv_cmd_buffer *cmd_buffer, uint32_t x, uint32_t y,
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uint32_t z, uint32_t first_task)
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uint32_t z)
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{
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uint64_t fake_ib_va = 0;
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const uint32_t view_mask = cmd_buffer->state.render.view_mask;
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const unsigned num_views = MAX2(1, util_bitcount(view_mask));
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unsigned ace_predication_size = num_views * 6; /* DISPATCH_TASKMESH_DIRECT_ACE size */
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if (first_task) {
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/* Pass this as the IB to the shader for emulating firstTask in task shaders. */
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uint32_t fake_ib_dwords[2] = {x, first_task};
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unsigned fake_ib_offset;
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radv_cmd_buffer_upload_data(cmd_buffer, 8, fake_ib_dwords, &fake_ib_offset);
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fake_ib_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + fake_ib_offset;
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}
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radv_emit_userdata_task(cmd_buffer, x, y, z, 0, first_task, fake_ib_va);
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radv_emit_userdata_mesh_first_task_0_draw_id_0(cmd_buffer);
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radv_emit_userdata_task(cmd_buffer, x, y, z, 0);
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radv_emit_userdata_mesh_draw_id_0(cmd_buffer);
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radv_cs_emit_compute_predication(&cmd_buffer->state, cmd_buffer->ace_internal.cs,
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cmd_buffer->mec_inv_pred_va, &cmd_buffer->mec_inv_pred_emitted,
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ace_predication_size);
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@ -8453,8 +8415,7 @@ radv_emit_direct_taskmesh_draw_packets(struct radv_cmd_buffer *cmd_buffer, uint3
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static void
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radv_emit_indirect_taskmesh_draw_packets(struct radv_cmd_buffer *cmd_buffer,
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const struct radv_draw_info *info, uint64_t nv_ib_va,
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uint32_t nv_ib_stride)
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const struct radv_draw_info *info)
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{
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const uint32_t view_mask = cmd_buffer->state.render.view_mask;
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struct radeon_winsys *ws = cmd_buffer->device->ws;
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@ -8510,8 +8471,7 @@ radv_emit_indirect_taskmesh_draw_packets(struct radv_cmd_buffer *cmd_buffer,
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}
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radv_cs_add_buffer(ws, cmd_buffer->ace_internal.cs, info->indirect->bo);
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radv_emit_userdata_task_ib_only(cmd_buffer, nv_ib_va, nv_ib_stride);
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radv_emit_userdata_mesh_first_task_0_draw_id_0(cmd_buffer);
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radv_emit_userdata_mesh_draw_id_0(cmd_buffer);
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radv_cs_emit_compute_predication(&cmd_buffer->state, cmd_buffer->ace_internal.cs,
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cmd_buffer->mec_inv_pred_va, &cmd_buffer->mec_inv_pred_emitted,
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ace_predication_size);
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@ -9274,9 +9234,9 @@ radv_CmdDrawMeshTasksEXT(VkCommandBuffer commandBuffer, uint32_t x, uint32_t y,
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return;
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if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) {
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radv_emit_direct_taskmesh_draw_packets(cmd_buffer, x, y, z, 0);
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radv_emit_direct_taskmesh_draw_packets(cmd_buffer, x, y, z);
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} else {
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radv_emit_direct_mesh_draw_packet(cmd_buffer, x, y, z, 0);
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radv_emit_direct_mesh_draw_packet(cmd_buffer, x, y, z);
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}
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radv_after_draw(cmd_buffer);
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@ -9307,7 +9267,7 @@ radv_CmdDrawMeshTasksIndirectEXT(VkCommandBuffer commandBuffer, VkBuffer _buffer
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return;
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if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) {
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radv_emit_indirect_taskmesh_draw_packets(cmd_buffer, &info, 0, 0);
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radv_emit_indirect_taskmesh_draw_packets(cmd_buffer, &info);
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} else {
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radv_emit_indirect_mesh_draw_packets(cmd_buffer, &info);
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}
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@ -9342,7 +9302,7 @@ radv_CmdDrawMeshTasksIndirectCountEXT(VkCommandBuffer commandBuffer, VkBuffer _b
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return;
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if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) {
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radv_emit_indirect_taskmesh_draw_packets(cmd_buffer, &info, 0, 0);
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radv_emit_indirect_taskmesh_draw_packets(cmd_buffer, &info);
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} else {
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radv_emit_indirect_mesh_draw_packets(cmd_buffer, &info);
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}
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@ -273,10 +273,10 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
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replacement = ac_nir_load_arg(b, &s->args->ac, s->args->ac.task_ring_entry);
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break;
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case nir_intrinsic_load_task_ib_addr:
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replacement = ac_nir_load_arg(b, &s->args->ac, s->args->task_ib_addr);
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replacement = nir_imm_zero(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
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break;
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case nir_intrinsic_load_task_ib_stride:
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replacement = ac_nir_load_arg(b, &s->args->ac, s->args->task_ib_stride);
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replacement = nir_imm_zero(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
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break;
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case nir_intrinsic_load_lshs_vertex_stride_amd: {
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unsigned io_num = stage == MESA_SHADER_VERTEX ?
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@ -594,39 +594,6 @@ radv_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage *fs_s
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return progress;
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}
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/* Emulates NV_mesh_shader first_task using first_vertex. */
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static bool
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radv_lower_ms_workgroup_id(nir_shader *nir)
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{
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nir_function_impl *impl = nir_shader_get_entrypoint(nir);
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bool progress = false;
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nir_builder b;
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nir_builder_init(&b, impl);
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic != nir_intrinsic_load_workgroup_id)
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continue;
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progress = true;
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b.cursor = nir_after_instr(instr);
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nir_ssa_def *x = nir_channel(&b, &intrin->dest.ssa, 0);
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nir_ssa_def *x_full = nir_iadd(&b, x, nir_load_first_vertex(&b));
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nir_ssa_def *v = nir_vector_insert_imm(&b, &intrin->dest.ssa, x_full, 0);
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nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa, v, v->parent_instr);
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}
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}
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nir_metadata preserved =
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progress ? (nir_metadata_block_index | nir_metadata_dominance) : nir_metadata_all;
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nir_metadata_preserve(impl, preserved);
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return progress;
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}
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static bool
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is_sincos(const nir_instr *instr, const void *_)
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{
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@ -889,9 +856,6 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_
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NIR_PASS(_, nir, nir_lower_compute_system_values, &csv_options);
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if (nir->info.stage == MESA_SHADER_MESH) {
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/* NV_mesh_shader: include first_task (aka. first_vertex) in workgroup ID. */
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NIR_PASS(_, nir, radv_lower_ms_workgroup_id);
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/* Mesh shaders only have a 1D "vertex index" which we use
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* as "workgroup index" to emulate the 3D workgroup ID.
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*/
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@ -1204,7 +1168,6 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta
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device->physical_device->rad_info.gfx_level, false);
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return true;
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} else if (nir->info.stage == MESA_SHADER_TASK) {
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ac_nir_apply_first_task_to_task_shader(nir);
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ac_nir_lower_task_outputs_to_mem(nir, AC_TASK_PAYLOAD_ENTRY_BYTES,
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device->physical_device->task_info.num_entries);
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return true;
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@ -108,7 +108,7 @@ count_tes_user_sgprs(const struct radv_pipeline_key *key)
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static uint8_t
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count_ms_user_sgprs(const struct radv_shader_info *info)
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{
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uint8_t count = 1 + 3; /* firstTask + num_work_groups[3] */
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uint8_t count = 3; /* num_work_groups[3] */
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if (info->vs.needs_draw_id)
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count++;
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@ -415,7 +415,6 @@ declare_tes_input_vgprs(struct radv_shader_args *args)
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static void
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declare_ms_input_sgprs(const struct radv_shader_info *info, struct radv_shader_args *args)
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{
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ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.base_vertex);
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ac_add_arg(&args->ac, AC_ARG_SGPR, 3, AC_ARG_INT, &args->ac.num_work_groups);
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if (info->vs.needs_draw_id) {
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ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.draw_id);
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@ -553,7 +552,7 @@ static void
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set_ms_input_locs(struct radv_shader_args *args, uint8_t *user_sgpr_idx)
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{
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unsigned vs_num =
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args->ac.base_vertex.used + 3 * args->ac.num_work_groups.used + args->ac.draw_id.used;
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3 * args->ac.num_work_groups.used + args->ac.draw_id.used;
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set_loc_shader(args, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
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if (args->ac.task_ring_entry.used)
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@ -664,8 +663,6 @@ radv_declare_shader_args(const struct radv_device *device, const struct radv_pip
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if (stage == MESA_SHADER_TASK) {
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ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.task_ring_entry);
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ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_INT, &args->task_ib_addr);
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ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->task_ib_stride);
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}
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for (int i = 0; i < 3; i++) {
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@ -947,10 +944,6 @@ radv_declare_shader_args(const struct radv_device *device, const struct radv_pip
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if (args->ac.task_ring_entry.used) {
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set_loc_shader(args, AC_UD_TASK_RING_ENTRY, &user_sgpr_idx, 1);
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}
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if (args->task_ib_addr.used) {
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assert(args->task_ib_stride.used);
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set_loc_shader(args, AC_UD_CS_TASK_IB, &user_sgpr_idx, 3);
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}
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break;
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case MESA_SHADER_VERTEX:
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if (args->ac.view_index.used)
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@ -51,10 +51,6 @@ struct radv_shader_args {
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struct ac_arg ngg_viewport_scale[2];
|
||||
struct ac_arg ngg_viewport_translate[2];
|
||||
|
||||
/* Task shaders */
|
||||
struct ac_arg task_ib_addr;
|
||||
struct ac_arg task_ib_stride;
|
||||
|
||||
/* Fragment shaders */
|
||||
struct ac_arg ps_epilog_pc;
|
||||
struct ac_arg ps_num_samples;
|
||||
|
|
|
|||
|
|
@ -514,7 +514,6 @@ gather_shader_info_mesh(const nir_shader *nir, struct radv_shader_info *info)
|
|||
* - drawing 1 input vertex ~ launching 1 mesh shader workgroup
|
||||
*
|
||||
* In the shader:
|
||||
* - base vertex ~ first workgroup index (firstTask in NV_mesh_shader)
|
||||
* - input vertex id ~ workgroup id (in 1D - shader needs to calculate in 3D)
|
||||
*
|
||||
* Notes:
|
||||
|
|
@ -711,10 +710,6 @@ gather_shader_info_task(const nir_shader *nir, struct radv_shader_info *info)
|
|||
* use them.
|
||||
*/
|
||||
|
||||
/* Needed to address the IB to read firstTask in NV_mesh_shader. */
|
||||
info->vs.needs_draw_id |=
|
||||
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_WORKGROUP_ID);
|
||||
|
||||
/* Needed to address the task draw/payload rings. */
|
||||
info->cs.uses_block_id[0] = true;
|
||||
info->cs.uses_block_id[1] = true;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue