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nv50/ir: only enable mul saturate on G200+

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Commit 44673512a8 enabled support for saturating fmul. However
experimentally this does not seem to work on the older chips. Restrict
the feature to G200 (NVA0) and later.

Reported-by: Pierre Moreau <pierre.morrow@free.fr>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90350
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit da136dc07d)
This commit is contained in:
Ilia Mirkin 2015-05-09 03:26:07 -04:00 • committed by Emil Velikov
parent d47d799b5f
commit 8a3ed2dee7
1 changed files with 4 additions and 1 deletions
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5
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
View file

@ -84,7 +84,7 @@ static const struct opProperties _initProps[] =
// neg abs not sat c[] s[], a[], imm
{ OP_ADD, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
{ OP_SUB, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
{ OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
{ OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
{ OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
{ OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
{ OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x1, 0x1, 0x0 }, // special constraint
@ -188,6 +188,9 @@ void TargetNV50::initOpInfo()
if (prop->mSat & 8)
opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
}
if (chipset >= 0xa0)
opInfo[OP_MUL].dstMods = NV50_IR_MOD_SAT;
}
unsigned int