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i965/gen9: Enable rep clears on gen9

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The (gen < 9) check in brw_clear() was too broad. It disabled all types
of fast color clears:
    a. singlesample rep clears
    b. singlesample MCS fast clears
    c. multisample MCS fast clears

The MCS clears are still buggy, but the rep clear works well. So let's
enable it.

Reviewed-by: Neil Roberts <neil@linux.intel.com>
This commit is contained in:
Chad Versace 2015-10-08 12:06:24 -07:00
parent dcd59a9e32
commit 8a0c85b258
2 changed files with 6 additions and 1 deletions
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2
src/mesa/drivers/dri/i965/brw_clear.c
View file

@ -241,7 +241,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
}
/* Clear color buffers with fast clear or at least rep16 writes. */
if (brw->gen >= 6 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) {
if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) {
if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) {
debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
mask &= ~BUFFER_BITS_COLOR;

5
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
View file

@ -451,6 +451,11 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS)
clear_type = REP_CLEAR;
if (brw->gen >= 9 && clear_type == FAST_CLEAR) {
perf_debug("fast MCS clears are disabled on gen9");
clear_type = REP_CLEAR;
}
/* We can't do scissored fast clears because of the restrictions on the
* fast clear rectangle size.
*/