diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 64580ef6dda..b1bb447f2c3 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1858,7 +1858,7 @@ swsb(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
       opcode == BRW_OPCODE_MATH || opcode == BRW_OPCODE_DPAS ||
       (devinfo->has_64bit_float_via_math_pipe &&
        inst_has_type(isa, inst, BRW_TYPE_DF));
-   const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, is_unordered, x);
+   const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, is_unordered, x, opcode);
    if (swsb.regdist)
       format(file, " %s@%d",
              (swsb.pipe == TGL_PIPE_FLOAT ? "F" :
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index d00b4990755..6487da7af0f 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -954,7 +954,8 @@ tgl_swsb_src_dep(struct tgl_swsb swsb)
  * SWSB annotation.
  */
 static inline uint32_t
-tgl_swsb_encode(const struct intel_device_info *devinfo, struct tgl_swsb swsb)
+tgl_swsb_encode(const struct intel_device_info *devinfo,
+                struct tgl_swsb swsb, enum opcode opcode)
 {
    if (!swsb.mode) {
       const unsigned pipe = devinfo->verx10 < 125 ? 0 :
@@ -1002,7 +1003,7 @@ tgl_swsb_encode(const struct intel_device_info *devinfo, struct tgl_swsb swsb)
  */
 static inline struct tgl_swsb
 tgl_swsb_decode(const struct intel_device_info *devinfo,
-                const bool is_unordered, const uint32_t x)
+                const bool is_unordered, const uint32_t x, enum opcode opcode)
 {
    if (devinfo->ver >= 20) {
       if (x & 0x300) {
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 16f34ed50ef..85cd1cf9e11 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -369,7 +369,7 @@ brw_inst_set_state(const struct brw_isa_info *isa,
    brw_inst_set_access_mode(devinfo, insn, state->access_mode);
    brw_inst_set_mask_control(devinfo, insn, state->mask_control);
    if (devinfo->ver >= 12)
-      brw_inst_set_swsb(devinfo, insn, tgl_swsb_encode(devinfo, state->swsb));
+      brw_inst_set_swsb(devinfo, insn, tgl_swsb_encode(devinfo, state->swsb, brw_inst_opcode(isa, insn)));
    brw_inst_set_saturate(devinfo, insn, state->saturate);
    brw_inst_set_pred_control(devinfo, insn, state->predicate);
    brw_inst_set_pred_inv(devinfo, insn, state->pred_inv);
diff --git a/src/intel/compiler/brw_gram.y b/src/intel/compiler/brw_gram.y
index 25daee0d382..85ef52cc2f6 100644
--- a/src/intel/compiler/brw_gram.y
+++ b/src/intel/compiler/brw_gram.y
@@ -291,8 +291,10 @@ i965_asm_set_instruction_options(struct brw_codegen *p,
 		brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
 					 options.no_dd_clear);
 	} else {
+		enum opcode opcode = brw_inst_opcode(p->isa, brw_last_inst);
 		brw_inst_set_swsb(p->devinfo, brw_last_inst,
-		                  tgl_swsb_encode(p->devinfo, options.depinfo));
+		                  tgl_swsb_encode(p->devinfo, options.depinfo,
+						  opcode));
 	}
 	brw_inst_set_debug_control(p->devinfo, brw_last_inst,
 			           options.debug_control);