mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-08 02:38:04 +02:00
vc4: Implement live intervals using a CFG.
Right now our CFG is always a trivial single basic block, but that will change when enable loops.
This commit is contained in:
Eric Anholt
parent
f2eb8e3052
commit
89918c1e74
6 changed files with 393 additions and 39 deletions
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@ -31,6 +31,7 @@ C_SOURCES := \
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vc4_opt_vpm.c \
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vc4_program.c \
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vc4_qir.c \
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vc4_qir_live_variables.c \
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vc4_qir_lower_uniforms.c \
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vc4_qir_schedule.c \
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vc4_qir_validate.c \
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@ -224,6 +224,53 @@ qir_writes_r4(struct qinst *inst)
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}
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}
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uint8_t
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qir_channels_written(struct qinst *inst)
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{
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if (qir_is_mul(inst)) {
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switch (inst->dst.pack) {
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case QPU_PACK_MUL_NOP:
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case QPU_PACK_MUL_8888:
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return 0xf;
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case QPU_PACK_MUL_8A:
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return 0x1;
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case QPU_PACK_MUL_8B:
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return 0x2;
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case QPU_PACK_MUL_8C:
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return 0x4;
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case QPU_PACK_MUL_8D:
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return 0x8;
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}
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} else {
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switch (inst->dst.pack) {
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case QPU_PACK_A_NOP:
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case QPU_PACK_A_8888:
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case QPU_PACK_A_8888_SAT:
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case QPU_PACK_A_32_SAT:
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return 0xf;
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case QPU_PACK_A_8A:
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case QPU_PACK_A_8A_SAT:
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return 0x1;
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case QPU_PACK_A_8B:
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case QPU_PACK_A_8B_SAT:
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return 0x2;
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case QPU_PACK_A_8C:
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case QPU_PACK_A_8C_SAT:
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return 0x4;
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case QPU_PACK_A_8D:
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case QPU_PACK_A_8D_SAT:
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return 0x8;
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case QPU_PACK_A_16A:
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case QPU_PACK_A_16A_SAT:
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return 0x3;
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case QPU_PACK_A_16B:
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case QPU_PACK_A_16B_SAT:
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return 0xc;
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}
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}
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unreachable("Bad pack field");
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}
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static void
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qir_print_reg(struct vc4_compile *c, struct qreg reg, bool write)
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{
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@ -38,6 +38,7 @@
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#include "vc4_screen.h"
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#include "vc4_qpu_defines.h"
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#include "vc4_qpu.h"
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#include "kernel/vc4_packet.h"
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#include "pipe/p_state.h"
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@ -353,6 +354,14 @@ struct qblock {
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struct qblock *successors[2];
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int index;
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/** @{ used by vc4_qir_live_variables.c */
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BITSET_WORD *def;
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BITSET_WORD *use;
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BITSET_WORD *live_in;
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BITSET_WORD *live_out;
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int start_ip, end_ip;
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/** @} */
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};
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struct vc4_compile {
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@ -422,6 +431,9 @@ struct vc4_compile {
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struct vc4_fs_key *fs_key;
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struct vc4_vs_key *vs_key;
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/* Live ranges of temps. */
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int *temp_start, *temp_end;
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uint32_t *uniform_data;
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enum quniform_contents *uniform_contents;
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uint32_t uniform_array_size;
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@ -488,6 +500,7 @@ struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst);
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struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst);
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struct qreg qir_get_temp(struct vc4_compile *c);
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void qir_calculate_live_intervals(struct vc4_compile *c);
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int qir_get_op_nsrc(enum qop qop);
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bool qir_reg_equals(struct qreg a, struct qreg b);
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bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
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@ -499,6 +512,7 @@ bool qir_is_float_input(struct qinst *inst);
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bool qir_depends_on_flags(struct qinst *inst);
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bool qir_writes_r4(struct qinst *inst);
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struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
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uint8_t qir_channels_written(struct qinst *inst);
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void qir_dump(struct vc4_compile *c);
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void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
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@ -667,7 +681,7 @@ qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1)
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struct qinst *a = qir_MOV_dest(c, t, src0);
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struct qinst *b = qir_MOV_dest(c, t, src1);
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a->cond = cond;
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b->cond = cond ^ 1;
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b->cond = qpu_cond_complement(cond);
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return t;
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}
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316
src/gallium/drivers/vc4/vc4_qir_live_variables.c
Normal file
316
src/gallium/drivers/vc4/vc4_qir_live_variables.c
Normal file
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@ -0,0 +1,316 @@
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/*
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* Copyright © 2012 Intel Corporation
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* Copyright © 2016 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#define MAX_INSTRUCTION (1 << 30)
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#include "util/ralloc.h"
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#include "util/register_allocate.h"
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#include "vc4_context.h"
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#include "vc4_qir.h"
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struct partial_update_state {
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struct qinst *insts[4];
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uint8_t channels;
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};
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static uint32_t
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int_hash(const void *key)
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{
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return _mesa_hash_data(key, sizeof(int));
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}
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static bool
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int_compare(const void *key1, const void *key2)
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{
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return *(const int *)key1 == *(const int *)key2;
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}
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static int
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qir_reg_to_var(struct qreg reg)
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{
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if (reg.file == QFILE_TEMP)
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return reg.index;
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return -1;
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}
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static void
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qir_setup_use(struct vc4_compile *c, struct qblock *block, int ip,
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struct qreg src)
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{
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int var = qir_reg_to_var(src);
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if (var == -1)
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return;
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c->temp_start[var] = MIN2(c->temp_start[var], ip);
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c->temp_end[var] = MAX2(c->temp_end[var], ip);
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/* The use[] bitset marks when the block makes
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* use of a variable without having completely
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* defined that variable within the block.
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*/
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if (!BITSET_TEST(block->def, var))
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BITSET_SET(block->use, var);
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}
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static struct partial_update_state *
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get_partial_update_state(struct hash_table *partial_update_ht,
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struct qinst *inst)
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{
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struct hash_entry *entry =
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_mesa_hash_table_search(partial_update_ht,
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&inst->dst.index);
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if (entry)
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return entry->data;
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struct partial_update_state *state =
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rzalloc(partial_update_ht, struct partial_update_state);
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_mesa_hash_table_insert(partial_update_ht, &inst->dst.index, state);
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return state;
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}
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static void
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qir_setup_def(struct vc4_compile *c, struct qblock *block, int ip,
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struct hash_table *partial_update_ht, struct qinst *inst)
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{
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/* The def[] bitset marks when an initialization in a
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* block completely screens off previous updates of
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* that variable.
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*/
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int var = qir_reg_to_var(inst->dst);
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if (var == -1)
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return;
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c->temp_start[var] = MIN2(c->temp_start[var], ip);
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c->temp_end[var] = MAX2(c->temp_end[var], ip);
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/* If we've already tracked this as a def, or already used it within
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* the block, there's nothing to do.
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*/
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if (BITSET_TEST(block->use, var) || BITSET_TEST(block->def, var))
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return;
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/* Easy, common case: unconditional full register update. */
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if (inst->cond == QPU_COND_ALWAYS && !inst->dst.pack) {
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BITSET_SET(block->def, var);
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return;
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}
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/* Finally, look at the condition code and packing and mark it as a
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* def. We need to make sure that we understand sequences
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* instructions like:
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*
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* mov.zs t0, t1
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* mov.zc t0, t2
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*
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* or:
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*
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* mmov t0.8a, t1
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* mmov t0.8b, t2
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* mmov t0.8c, t3
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* mmov t0.8d, t4
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*
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* as defining the temp within the block, because otherwise dst's live
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* range will get extended up the control flow to the top of the
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* program.
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*/
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struct partial_update_state *state =
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get_partial_update_state(partial_update_ht, inst);
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uint8_t mask = qir_channels_written(inst);
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if (inst->cond == QPU_COND_ALWAYS) {
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state->channels |= mask;
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} else {
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for (int i = 0; i < 4; i++) {
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if (!(mask & (1 << i)))
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continue;
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if (state->insts[i] &&
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state->insts[i]->cond ==
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qpu_cond_complement(inst->cond))
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state->channels |= 1 << i;
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else
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state->insts[i] = inst;
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}
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}
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if (state->channels == 0xf)
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BITSET_SET(block->def, var);
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}
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static void
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sf_state_clear(struct hash_table *partial_update_ht)
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{
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struct hash_entry *entry;
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hash_table_foreach(partial_update_ht, entry) {
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struct partial_update_state *state = entry->data;
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for (int i = 0; i < 4; i++) {
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if (state->insts[i] && state->insts[i]->cond)
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state->insts[i] = NULL;
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}
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}
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}
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/* Sets up the def/use arrays for when variables are used-before-defined or
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* defined-before-used in the block.
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*
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* Also initializes the temp_start/temp_end to cover just the instruction IPs
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* where the variable is used, which will be extended later in
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* qir_compute_start_end().
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*/
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static void
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qir_setup_def_use(struct vc4_compile *c)
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{
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struct hash_table *partial_update_ht =
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_mesa_hash_table_create(c, int_hash, int_compare);
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int ip = 0;
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qir_for_each_block(block, c) {
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block->start_ip = ip;
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_mesa_hash_table_clear(partial_update_ht, NULL);
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qir_for_each_inst(inst, block) {
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for (int i = 0; i < qir_get_op_nsrc(inst->op); i++)
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qir_setup_use(c, block, ip, inst->src[i]);
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qir_setup_def(c, block, ip, partial_update_ht, inst);
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if (inst->sf)
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sf_state_clear(partial_update_ht);
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switch (inst->op) {
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case QOP_FRAG_Z:
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case QOP_FRAG_W:
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/* The payload registers have values
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* implicitly loaded at the start of the
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* program.
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*/
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if (inst->dst.file == QFILE_TEMP)
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c->temp_start[inst->dst.index] = 0;
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break;
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default:
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break;
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}
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ip++;
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}
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block->end_ip = ip;
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}
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_mesa_hash_table_destroy(partial_update_ht, NULL);
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}
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static bool
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qir_live_variables_dataflow(struct vc4_compile *c, int bitset_words)
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{
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bool cont = false;
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qir_for_each_block_rev(block, c) {
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/* Update live_out: Any successor using the variable
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* on entrance needs us to have the variable live on
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* exit.
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*/
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qir_for_each_successor(succ, block) {
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_live_out = (succ->live_in[i] &
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~block->live_out[i]);
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if (new_live_out) {
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block->live_out[i] |= new_live_out;
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cont = true;
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}
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}
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}
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/* Update live_in */
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_live_in = (block->use[i] |
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(block->live_out[i] &
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~block->def[i]));
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if (new_live_in & ~block->live_in[i]) {
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block->live_in[i] |= new_live_in;
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cont = true;
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}
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}
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}
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return cont;
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}
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/**
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* Extend the start/end ranges for each variable to account for the
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* new information calculated from control flow.
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*/
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static void
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qir_compute_start_end(struct vc4_compile *c, int num_vars)
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{
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qir_for_each_block(block, c) {
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for (int i = 0; i < num_vars; i++) {
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if (BITSET_TEST(block->live_in, i)) {
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c->temp_start[i] = MIN2(c->temp_start[i],
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block->start_ip);
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c->temp_end[i] = MAX2(c->temp_end[i],
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block->start_ip);
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}
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if (BITSET_TEST(block->live_out, i)) {
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c->temp_start[i] = MIN2(c->temp_start[i],
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block->end_ip);
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c->temp_end[i] = MAX2(c->temp_end[i],
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block->end_ip);
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}
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}
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}
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}
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void
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qir_calculate_live_intervals(struct vc4_compile *c)
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{
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int bitset_words = BITSET_WORDS(c->num_temps);
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c->temp_start = reralloc(c, c->temp_start, int, c->num_temps);
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c->temp_end = reralloc(c, c->temp_end, int, c->num_temps);
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for (int i = 0; i < c->num_temps; i++) {
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c->temp_start[i] = MAX_INSTRUCTION;
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c->temp_end[i] = -1;
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}
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qir_for_each_block(block, c) {
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block->def = reralloc(c, block->def, BITSET_WORD, bitset_words);
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block->use = reralloc(c, block->use, BITSET_WORD, bitset_words);
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block->live_in = reralloc(c, block->live_in, BITSET_WORD, bitset_words);
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block->live_out = reralloc(c, block->live_out, BITSET_WORD, bitset_words);
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}
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qir_setup_def_use(c);
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while (qir_live_variables_dataflow(c, bitset_words))
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;
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qir_compute_start_end(c, c->num_temps);
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}
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@ -153,6 +153,12 @@ bool qpu_inst_is_tlb(uint64_t inst) ATTRIBUTE_CONST;
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int qpu_num_sf_accesses(uint64_t inst) ATTRIBUTE_CONST;
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void qpu_serialize_one_inst(struct vc4_compile *c, uint64_t inst);
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static inline enum qpu_cond
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qpu_cond_complement(enum qpu_cond cond)
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{
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return cond ^ 1;
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}
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static inline uint64_t
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qpu_load_imm_f(struct qpu_reg dst, float val)
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{
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@ -175,14 +175,9 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
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{
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struct node_to_temp_map map[c->num_temps];
|
||||
uint32_t temp_to_node[c->num_temps];
|
||||
uint32_t def[c->num_temps];
|
||||
uint32_t use[c->num_temps];
|
||||
uint8_t class_bits[c->num_temps];
|
||||
struct qpu_reg *temp_registers = calloc(c->num_temps,
|
||||
sizeof(*temp_registers));
|
||||
for (int i = 0; i < ARRAY_SIZE(def); i++)
|
||||
def[i] = ~0;
|
||||
memset(use, 0, sizeof(use));
|
||||
|
||||
/* If things aren't ever written (undefined values), just read from
|
||||
* r0.
|
||||
|
|
@ -195,38 +190,12 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
|
|||
struct ra_graph *g = ra_alloc_interference_graph(vc4->regs,
|
||||
c->num_temps);
|
||||
|
||||
/* Compute the live ranges so we can figure out interference.
|
||||
*/
|
||||
uint32_t ip = 0;
|
||||
qir_for_each_inst_inorder(inst, c) {
|
||||
if (inst->dst.file == QFILE_TEMP) {
|
||||
def[inst->dst.index] = MIN2(ip, def[inst->dst.index]);
|
||||
use[inst->dst.index] = ip;
|
||||
}
|
||||
|
||||
for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
|
||||
if (inst->src[i].file == QFILE_TEMP)
|
||||
use[inst->src[i].index] = ip;
|
||||
}
|
||||
|
||||
switch (inst->op) {
|
||||
case QOP_FRAG_Z:
|
||||
case QOP_FRAG_W:
|
||||
/* The payload registers have values implicitly loaded
|
||||
* at the start of the program.
|
||||
*/
|
||||
def[inst->dst.index] = 0;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
ip++;
|
||||
}
|
||||
/* Compute the live ranges so we can figure out interference. */
|
||||
qir_calculate_live_intervals(c);
|
||||
|
||||
for (uint32_t i = 0; i < c->num_temps; i++) {
|
||||
map[i].temp = i;
|
||||
map[i].priority = use[i] - def[i];
|
||||
map[i].priority = c->temp_end[i] - c->temp_start[i];
|
||||
}
|
||||
qsort(map, c->num_temps, sizeof(map[0]), node_to_temp_priority);
|
||||
for (uint32_t i = 0; i < c->num_temps; i++) {
|
||||
|
|
@ -241,7 +210,7 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
|
|||
CLASS_BIT_A | CLASS_BIT_B_OR_ACC | CLASS_BIT_R4,
|
||||
sizeof(class_bits));
|
||||
|
||||
ip = 0;
|
||||
int ip = 0;
|
||||
qir_for_each_inst_inorder(inst, c) {
|
||||
if (qir_writes_r4(inst)) {
|
||||
/* This instruction writes r4 (and optionally moves
|
||||
|
|
@ -249,7 +218,7 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
|
|||
* stored in r4 across it.
|
||||
*/
|
||||
for (int i = 0; i < c->num_temps; i++) {
|
||||
if (def[i] < ip && use[i] > ip)
|
||||
if (c->temp_start[i] < ip && c->temp_end[i] > ip)
|
||||
class_bits[i] &= ~CLASS_BIT_R4;
|
||||
}
|
||||
} else {
|
||||
|
|
@ -328,7 +297,8 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
|
|||
|
||||
for (uint32_t i = 0; i < c->num_temps; i++) {
|
||||
for (uint32_t j = i + 1; j < c->num_temps; j++) {
|
||||
if (!(def[i] >= use[j] || def[j] >= use[i])) {
|
||||
if (!(c->temp_start[i] >= c->temp_end[j] ||
|
||||
c->temp_start[j] >= c->temp_end[i])) {
|
||||
ra_add_node_interference(g,
|
||||
temp_to_node[i],
|
||||
temp_to_node[j]);
|
||||
|
|
@ -349,7 +319,7 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
|
|||
/* If the value's never used, just write to the NOP register
|
||||
* for clarity in debug output.
|
||||
*/
|
||||
if (def[i] == use[i])
|
||||
if (c->temp_start[i] == c->temp_end[i])
|
||||
temp_registers[i] = qpu_ra(QPU_W_NOP);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue