fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-06 04:30:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: store gfx/compute bound shaders on command buffer state
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36512>
This commit is contained in:
Lionel Landwerlin 2025-02-11 12:49:11 +02:00 • committed by Marge Bot
parent 094ddc35cc
commit 8966088cc5
9 changed files with 382 additions and 353 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
src/intel/vulkan/anv_cmd_buffer.c
View file

@ -503,9 +503,9 @@ anv_cmd_buffer_set_ray_query_buffer(struct anv_cmd_buffer *cmd_buffer,
* state appropriately.
*/
static void
anv_cmd_buffer_flush_pipeline_state(struct anv_cmd_buffer *cmd_buffer,
struct anv_graphics_pipeline *old_pipeline,
struct anv_graphics_pipeline *new_pipeline)
anv_cmd_buffer_flush_pipeline_hw_state(struct anv_cmd_buffer *cmd_buffer,
struct anv_graphics_pipeline *old_pipeline,
struct anv_graphics_pipeline *new_pipeline)
{
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
struct anv_gfx_dynamic_state *hw_state = &gfx->dyn_state;
@ -681,11 +681,12 @@ void anv_CmdBindPipeline(
if (cmd_buffer->state.compute.base.pipeline == pipeline)
return;
cmd_buffer->state.compute.base.pipeline = pipeline;
cmd_buffer->state.compute.pipeline_dirty = true;
struct anv_compute_pipeline *compute_pipeline =
anv_pipeline_to_compute(pipeline);
cmd_buffer->state.compute.shader = compute_pipeline->cs;
cmd_buffer->state.compute.pipeline_dirty = true;
set_dirty_for_bind_map(cmd_buffer, MESA_SHADER_COMPUTE,
&compute_pipeline->cs->bind_map);
@ -711,11 +712,17 @@ void anv_CmdBindPipeline(
cmd_buffer->state.gfx.base.pipeline == NULL ? NULL :
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
cmd_buffer->state.gfx.base.pipeline = pipeline;
cmd_buffer->state.gfx.dirty |=
get_pipeline_dirty_stages(cmd_buffer->device,
old_pipeline, new_pipeline);
STATIC_ASSERT(sizeof(cmd_buffer->state.gfx.shaders) ==
sizeof(new_pipeline->base.shaders));
memcpy(cmd_buffer->state.gfx.shaders,
new_pipeline->base.shaders,
sizeof(cmd_buffer->state.gfx.shaders));
cmd_buffer->state.gfx.active_stages = pipeline->active_stages;
anv_foreach_stage(stage, new_pipeline->base.base.active_stages) {
set_dirty_for_bind_map(cmd_buffer, stage,
&new_pipeline->base.shaders[stage]->bind_map);
@ -757,7 +764,13 @@ void anv_CmdBindPipeline(
}
}
anv_cmd_buffer_flush_pipeline_state(cmd_buffer, old_pipeline, new_pipeline);
cmd_buffer->state.gfx.min_sample_shading = new_pipeline->min_sample_shading;
cmd_buffer->state.gfx.sample_shading_enable = new_pipeline->sample_shading_enable;
cmd_buffer->state.gfx.instance_multiplier = new_pipeline->instance_multiplier;
cmd_buffer->state.gfx.primitive_id_index = new_pipeline->primitive_id_index;
cmd_buffer->state.gfx.first_vue_slot = new_pipeline->first_vue_slot;
anv_cmd_buffer_flush_pipeline_hw_state(cmd_buffer, old_pipeline, new_pipeline);
break;
}
@ -765,7 +778,6 @@ void anv_CmdBindPipeline(
if (cmd_buffer->state.rt.base.pipeline == pipeline)
return;
cmd_buffer->state.rt.base.pipeline = pipeline;
cmd_buffer->state.rt.pipeline_dirty = true;
struct anv_ray_tracing_pipeline *rt_pipeline =
@ -788,6 +800,8 @@ void anv_CmdBindPipeline(
break;
}
state->pipeline = pipeline;
if (pipeline->ray_queries > 0)
anv_cmd_buffer_set_ray_query_buffer(cmd_buffer, state, pipeline, stages);
}
@ -1332,12 +1346,11 @@ struct anv_state
anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
{
const struct intel_device_info *devinfo = cmd_buffer->device->info;
struct anv_cmd_pipeline_state *pipe_state = &cmd_buffer->state.compute.base;
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
struct anv_cmd_pipeline_state *pipe_state = &comp_state->base;
struct anv_push_constants *data = &pipe_state->push_constants;
struct anv_compute_pipeline *pipeline =
anv_pipeline_to_compute(cmd_buffer->state.compute.base.pipeline);
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct anv_push_range *range = &pipeline->cs->bind_map.push_ranges[0];
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(comp_state);
const struct anv_push_range *range = &comp_state->shader->bind_map.push_ranges[0];
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);

6
src/intel/vulkan/anv_pipeline.c
View file

@ -2877,8 +2877,10 @@ anv_graphics_pipeline_emit(struct anv_graphics_pipeline *pipeline,
pipeline->view_mask = state->rp->view_mask;
if (anv_pipeline_is_primitive(pipeline)) {
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_vs_prog_data *vs_prog_data =
get_pipeline_vs_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data =
get_pipeline_wm_prog_data(pipeline);
/* The total number of vertex elements we need to program. We might need
* a couple more to implement some of the draw parameters.

63
src/intel/vulkan/anv_private.h
View file

@ -4107,6 +4107,26 @@ enum anv_depth_reg_mode {
struct anv_cmd_graphics_state {
struct anv_cmd_pipeline_state base;
/* Shaders bound */
struct anv_shader_bin *shaders[ANV_GRAPHICS_SHADER_STAGE_COUNT];
/* Bitfield of valid entries in the shaders array */
VkShaderStageFlags active_stages;
uint32_t vs_source_hash;
uint32_t fs_source_hash;
/* Pipeline information */
uint32_t instance_multiplier;
bool kill_pixel;
bool uses_xfb;
bool sample_shading_enable;
float min_sample_shading;
uint32_t primitive_id_index;
uint32_t first_vue_slot;
/* Render pass information */
VkRenderingFlags rendering_flags;
VkRect2D render_area;
uint32_t layer_count;
@ -4200,6 +4220,8 @@ struct anv_cmd_graphics_state {
struct anv_cmd_compute_state {
struct anv_cmd_pipeline_state base;
struct anv_shader_bin *shader;
bool pipeline_dirty;
uint32_t scratch_size;
@ -4598,6 +4620,13 @@ anv_cmd_buffer_descriptor_buffer_address(struct anv_cmd_buffer *cmd_buffer,
return cmd_buffer->state.descriptor_buffers.address[buffer_index];
}
static inline bool
anv_cmd_buffer_has_gfx_stage(struct anv_cmd_buffer *cmd_buffer,
gl_shader_stage stage)
{
return cmd_buffer->state.gfx.shaders[stage] != NULL;
}
VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
@ -5277,6 +5306,13 @@ anv_pipeline_is_mesh(const struct anv_graphics_pipeline *pipeline)
return anv_pipeline_has_stage(pipeline, MESA_SHADER_MESH);
}
static inline bool
anv_gfx_has_stage(const struct anv_cmd_graphics_state *gfx,
gl_shader_stage stage)
{
return (gfx->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
}
static inline bool
anv_gfx_all_color_write_masked(const struct anv_cmd_graphics_state *gfx,
const struct vk_dynamic_graphics_state *dyn)
@ -5310,7 +5346,8 @@ anv_cmd_graphic_state_update_has_uint_rt(struct anv_cmd_graphics_state *state)
#define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
static inline const struct brw_##prefix##_prog_data * \
get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
get_pipeline_##prefix##_prog_data( \
const struct anv_graphics_pipeline *pipeline) \
{ \
if (anv_pipeline_has_stage(pipeline, stage)) { \
return (const struct brw_##prefix##_prog_data *) \
@ -5318,6 +5355,18 @@ get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
} else { \
return NULL; \
} \
} \
\
static inline const struct brw_##prefix##_prog_data * \
get_gfx_##prefix##_prog_data( \
const struct anv_cmd_graphics_state *gfx) \
{ \
if (anv_gfx_has_stage(gfx, stage)) { \
return (const struct brw_##prefix##_prog_data *) \
(gfx)->shaders[stage]->prog_data; \
} else { \
return NULL; \
} \
}
ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
@ -5329,21 +5378,21 @@ ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(mesh, MESA_SHADER_MESH)
ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(task, MESA_SHADER_TASK)
static inline const struct brw_cs_prog_data *
get_cs_prog_data(const struct anv_compute_pipeline *pipeline)
get_cs_prog_data(const struct anv_cmd_compute_state *comp_state)
{
assert(pipeline->cs);
return (const struct brw_cs_prog_data *) pipeline->cs->prog_data;
assert(comp_state->shader);
return (const struct brw_cs_prog_data *) comp_state->shader->prog_data;
}
static inline const struct brw_vue_prog_data *
anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline *pipeline)
{
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
return &get_gs_prog_data(pipeline)->base;
return &get_pipeline_gs_prog_data(pipeline)->base;
else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
return &get_tes_prog_data(pipeline)->base;
return &get_pipeline_tes_prog_data(pipeline)->base;
else
return &get_vs_prog_data(pipeline)->base;
return &get_pipeline_vs_prog_data(pipeline)->base;
}
VkResult

62
src/intel/vulkan/genX_cmd_compute.c
View file

@ -104,11 +104,11 @@ cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_device *device = cmd_buffer->device;
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
const UNUSED struct intel_device_info *devinfo = cmd_buffer->device->info;
struct anv_compute_pipeline *pipeline =
anv_pipeline_to_compute(comp_state->base.pipeline);
const UNUSED struct intel_device_info *devinfo = cmd_buffer->device->info;
assert(pipeline->cs);
assert(comp_state->shader);
genX(cmd_buffer_config_l3)(cmd_buffer,
pipeline->cs->prog_data->total_shared > 0 ?
@ -145,7 +145,7 @@ cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->base.batch);
#if GFX_VERx10 >= 125
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(comp_state);
genX(cmd_buffer_ensure_cfe_state)(cmd_buffer, prog_data->base.total_scratch);
#endif
@ -178,7 +178,7 @@ cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer,
&cmd_buffer->state.compute.base,
VK_SHADER_STAGE_COMPUTE_BIT,
(const struct anv_shader_bin **)&pipeline->cs, 1);
(const struct anv_shader_bin **)&comp_state->shader, 1);
cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
#if GFX_VERx10 < 125
@ -317,9 +317,8 @@ compute_load_indirect_params(struct anv_cmd_buffer *cmd_buffer,
const uint32_t mocs = isl_mocs(&cmd_buffer->device->isl_dev, 0, false);
mi_builder_set_mocs(&b, mocs);
struct anv_compute_pipeline *pipeline =
anv_pipeline_to_compute(cmd_buffer->state.compute.base.pipeline);
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(comp_state);
assert(util_is_power_of_two_or_zero(prog_data->local_size[0]));
size_x = mi_udiv32_imm(&b, size_x, prog_data->local_size[0]);
@ -436,7 +435,6 @@ compute_update_async_threads_limit(struct anv_cmd_buffer *cmd_buffer,
static inline void
emit_indirect_compute_walker(struct anv_cmd_buffer *cmd_buffer,
const struct anv_shader_bin *shader,
const struct brw_cs_prog_data *prog_data,
struct anv_address indirect_addr)
{
@ -483,8 +481,8 @@ emit_indirect_compute_walker(struct anv_cmd_buffer *cmd_buffer,
.ExecutionMask = dispatch.right_mask,
.PostSync.MOCS = anv_mocs(cmd_buffer->device, NULL, 0),
.InterfaceDescriptor =
get_interface_descriptor_data(cmd_buffer, shader, prog_data,
&dispatch),
get_interface_descriptor_data(cmd_buffer, comp_state->shader,
prog_data, &dispatch),
.EmitInlineParameter = prog_data->uses_inline_data,
.InlineData = {
[ANV_INLINE_PARAM_PUSH_ADDRESS_OFFSET / 4 + 0] = push_addr64 & 0xffffffff,
@ -511,7 +509,6 @@ emit_indirect_compute_walker(struct anv_cmd_buffer *cmd_buffer,
static inline void
emit_compute_walker(struct anv_cmd_buffer *cmd_buffer,
const struct anv_compute_pipeline *pipeline,
struct anv_address indirect_addr,
const struct brw_cs_prog_data *prog_data,
struct intel_cs_dispatch_info dispatch,
@ -555,10 +552,10 @@ emit_compute_walker(struct anv_cmd_buffer *cmd_buffer,
.ThreadGroupIDZDimension = groupCountZ,
.ExecutionMask = dispatch.right_mask,
.PostSync = {
.MOCS = anv_mocs(pipeline->base.device, NULL, 0),
.MOCS = anv_mocs(cmd_buffer->device, NULL, 0),
},
.InterfaceDescriptor =
get_interface_descriptor_data(cmd_buffer, pipeline->cs,
get_interface_descriptor_data(cmd_buffer, comp_state->shader,
prog_data, &dispatch),
.EmitInlineParameter = prog_data->uses_inline_data,
.InlineData = {
@ -593,14 +590,14 @@ emit_compute_walker(struct anv_cmd_buffer *cmd_buffer,
static inline void
emit_gpgpu_walker(struct anv_cmd_buffer *cmd_buffer,
const struct anv_compute_pipeline *pipeline, bool indirect,
bool indirect,
const struct brw_cs_prog_data *prog_data,
uint32_t groupCountX, uint32_t groupCountY,
uint32_t groupCountZ)
{
const bool predicate = cmd_buffer->state.conditional_render_enabled;
const struct intel_device_info *devinfo = pipeline->base.device->info;
const struct intel_device_info *devinfo = cmd_buffer->device->info;
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, prog_data, NULL);
@ -625,7 +622,6 @@ emit_gpgpu_walker(struct anv_cmd_buffer *cmd_buffer,
static inline void
emit_cs_walker(struct anv_cmd_buffer *cmd_buffer,
const struct anv_compute_pipeline *pipeline,
const struct brw_cs_prog_data *prog_data,
struct intel_cs_dispatch_info dispatch,
struct anv_address indirect_addr,
@ -650,7 +646,7 @@ emit_cs_walker(struct anv_cmd_buffer *cmd_buffer,
*/
if (is_indirect && !is_unaligned_size_x &&
cmd_buffer->device->info->has_indirect_unroll) {
emit_indirect_compute_walker(cmd_buffer, pipeline->cs, prog_data,
emit_indirect_compute_walker(cmd_buffer, prog_data,
indirect_addr);
return;
}
@ -661,10 +657,10 @@ emit_cs_walker(struct anv_cmd_buffer *cmd_buffer,
is_unaligned_size_x);
#if GFX_VERx10 >= 125
emit_compute_walker(cmd_buffer, pipeline, indirect_addr, prog_data,
emit_compute_walker(cmd_buffer, indirect_addr, prog_data,
dispatch, groupCountX, groupCountY, groupCountZ);
#else
emit_gpgpu_walker(cmd_buffer, pipeline, is_indirect, prog_data,
emit_gpgpu_walker(cmd_buffer, is_indirect, prog_data,
groupCountX, groupCountY, groupCountZ);
#endif
}
@ -679,9 +675,8 @@ void genX(CmdDispatchBase)(
uint32_t groupCountZ)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_compute_pipeline *pipeline =
anv_pipeline_to_compute(cmd_buffer->state.compute.base.pipeline);
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(comp_state);
struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(cmd_buffer->device->info, prog_data, NULL);
@ -709,7 +704,7 @@ void genX(CmdDispatchBase)(
genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, true);
emit_cs_walker(cmd_buffer, pipeline, prog_data, dispatch,
emit_cs_walker(cmd_buffer, prog_data, dispatch,
ANV_NULL_ADDRESS /* no indirect data */,
groupCountX, groupCountY, groupCountZ,
false);
@ -733,9 +728,8 @@ emit_unaligned_cs_walker(
struct intel_cs_dispatch_info dispatch)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_compute_pipeline *pipeline =
anv_pipeline_to_compute(cmd_buffer->state.compute.base.pipeline);
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(comp_state);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@ -770,7 +764,7 @@ emit_unaligned_cs_walker(
genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
#if GFX_VERx10 >= 125
emit_compute_walker(cmd_buffer, pipeline, ANV_NULL_ADDRESS, prog_data,
emit_compute_walker(cmd_buffer, ANV_NULL_ADDRESS, prog_data,
dispatch, groupCountX, groupCountY, groupCountZ);
#endif
@ -798,9 +792,8 @@ genX(cmd_dispatch_unaligned)(
uint32_t invocations_z)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_compute_pipeline *pipeline =
anv_pipeline_to_compute(cmd_buffer->state.compute.base.pipeline);
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(comp_state);
/* Group X can be unaligned for RT dispatches. */
uint32_t groupCountX = invocations_x / prog_data->local_size[0];
@ -849,9 +842,8 @@ genX(cmd_buffer_dispatch_indirect)(struct anv_cmd_buffer *cmd_buffer,
struct anv_address indirect_addr,
bool is_unaligned_size_x)
{
struct anv_compute_pipeline *pipeline =
anv_pipeline_to_compute(cmd_buffer->state.compute.base.pipeline);
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(comp_state);
UNUSED struct anv_batch *batch = &cmd_buffer->batch;
struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(cmd_buffer->device->info, prog_data, NULL);
@ -876,8 +868,8 @@ genX(cmd_buffer_dispatch_indirect)(struct anv_cmd_buffer *cmd_buffer,
genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, true);
emit_cs_walker(cmd_buffer, pipeline, prog_data, dispatch, indirect_addr, 0,
0, 0, is_unaligned_size_x);
emit_cs_walker(cmd_buffer, prog_data, dispatch, indirect_addr,
0, 0, 0, is_unaligned_size_x);
genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, false);

268
src/intel/vulkan/genX_cmd_draw.c
View file

@ -38,9 +38,8 @@
static void
cmd_buffer_alloc_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
VkShaderStageFlags stages = pipeline->base.base.active_stages;
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
VkShaderStageFlags stages = gfx->active_stages;
/* In order to avoid thrash, we assume that vertex and fragment stages
* always exist. In the rare case where one is missing *and* the other
@ -48,7 +47,7 @@ cmd_buffer_alloc_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer)
* seems more important.
*/
stages |= VK_SHADER_STAGE_FRAGMENT_BIT;
if (anv_pipeline_is_primitive(pipeline))
if (anv_gfx_has_stage(gfx, MESA_SHADER_VERTEX))
stages |= VK_SHADER_STAGE_VERTEX_BIT;
if (stages == cmd_buffer->state.gfx.push_constant_stages)
@ -57,7 +56,7 @@ cmd_buffer_alloc_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer)
unsigned push_constant_kb;
const struct intel_device_info *devinfo = cmd_buffer->device->info;
if (anv_pipeline_is_mesh(pipeline))
if (anv_gfx_has_stage(gfx, MESA_SHADER_MESH))
push_constant_kb = devinfo->mesh_max_constant_urb_size_kb;
else
push_constant_kb = devinfo->max_constant_urb_size_kb;
@ -316,9 +315,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
struct anv_address *buffers,
unsigned buffer_count)
{
const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
const struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(gfx_state->base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
static const uint32_t push_constant_opcodes[] = {
[MESA_SHADER_VERTEX] = 21,
@ -347,9 +344,9 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
*/
c.MOCS = mocs;
if (anv_pipeline_has_stage(pipeline, stage)) {
if (anv_gfx_has_stage(gfx, stage)) {
const struct anv_pipeline_bind_map *bind_map =
&pipeline->base.shaders[stage]->bind_map;
&gfx->shaders[stage]->bind_map;
/* The Skylake PRM contains the following restriction:
*
@ -396,14 +393,12 @@ cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer *cmd_buffer,
return;
}
const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
const struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(gfx_state->base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
gl_shader_stage stage = vk_to_mesa_shader_stage(shader_mask);
const struct anv_pipeline_bind_map *bind_map =
&pipeline->base.shaders[stage]->bind_map;
&gfx->shaders[stage]->bind_map;
uint32_t *dw;
const uint32_t buffer_mask = (1 << buffer_count) - 1;
@ -433,9 +428,7 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
VkShaderStageFlags dirty_stages)
{
VkShaderStageFlags flushed = 0;
struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
const struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(gfx_state->base.pipeline);
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
#if GFX_VER >= 12
uint32_t nobuffer_stages = 0;
@ -443,13 +436,13 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
/* Compute robust pushed register access mask for each stage. */
anv_foreach_stage(stage, dirty_stages) {
if (!anv_pipeline_has_stage(pipeline, stage))
if (!anv_gfx_has_stage(gfx, stage))
continue;
const struct anv_shader_bin *shader = pipeline->base.shaders[stage];
const struct anv_shader_bin *shader = gfx->shaders[stage];
if (shader->prog_data->zero_push_reg) {
const struct anv_pipeline_bind_map *bind_map = &shader->bind_map;
struct anv_push_constants *push = &gfx_state->base.push_constants;
struct anv_push_constants *push = &gfx->base.push_constants;
push->gfx.push_reg_mask[stage] = 0;
/* Start of the current range in the shader, relative to the start of
@ -480,7 +473,7 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
cmd_buffer->state.push_constants_dirty |=
mesa_to_vk_shader_stage(stage);
gfx_state->base.push_constants_data_dirty = true;
gfx->base.push_constants_data_dirty = true;
range_start_reg += range->length;
}
@ -494,12 +487,12 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
* Always reallocate on gfx9, gfx11 to fix push constant related flaky tests.
* See https://gitlab.freedesktop.org/mesa/mesa/-/issues/11064
*/
if (gfx_state->base.push_constants_data_dirty || GFX_VER < 12)
gfx_state->base.push_constants_state = ANV_STATE_NULL;
if (gfx->base.push_constants_data_dirty || GFX_VER < 12)
gfx->base.push_constants_state = ANV_STATE_NULL;
#if GFX_VERx10 >= 125
const struct brw_mesh_prog_data *mesh_prog_data =
get_mesh_prog_data(pipeline);
get_gfx_mesh_prog_data(gfx);
#endif
anv_foreach_stage(stage, dirty_stages) {
@ -508,8 +501,8 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
UNUSED uint32_t max_push_range = 0;
struct anv_address buffers[4] = {};
if (anv_pipeline_has_stage(pipeline, stage)) {
const struct anv_shader_bin *shader = pipeline->base.shaders[stage];
if (anv_gfx_has_stage(gfx, stage)) {
const struct anv_shader_bin *shader = gfx->shaders[stage];
const struct anv_pipeline_bind_map *bind_map = &shader->bind_map;
/* We have to gather buffer addresses as a second step because the
@ -584,30 +577,29 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
#endif
cmd_buffer->state.push_constants_dirty &= ~flushed;
gfx_state->base.push_constants_data_dirty = false;
gfx->base.push_constants_data_dirty = false;
}
#if GFX_VERx10 >= 125
static inline uint64_t
get_mesh_task_push_addr64(struct anv_cmd_buffer *cmd_buffer,
const struct anv_graphics_pipeline *pipeline,
struct anv_cmd_graphics_state *gfx,
gl_shader_stage stage)
{
struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
const struct anv_shader_bin *shader = pipeline->base.shaders[stage];
const struct anv_shader_bin *shader = gfx->shaders[stage];
const struct anv_pipeline_bind_map *bind_map = &shader->bind_map;
if (bind_map->push_ranges[0].length == 0)
return 0;
if (gfx_state->base.push_constants_state.alloc_size == 0) {
gfx_state->base.push_constants_state =
if (gfx->base.push_constants_state.alloc_size == 0) {
gfx->base.push_constants_state =
anv_cmd_buffer_gfx_push_constants(cmd_buffer);
}
return anv_address_physical(
anv_address_add(
anv_cmd_buffer_gfx_push_constants_state_address(cmd_buffer,
gfx_state->base.push_constants_state),
anv_cmd_buffer_gfx_push_constants_state_address(
cmd_buffer, gfx->base.push_constants_state),
bind_map->push_ranges[0].start * 32));
}
@ -615,14 +607,12 @@ static void
cmd_buffer_flush_mesh_inline_data(struct anv_cmd_buffer *cmd_buffer,
VkShaderStageFlags dirty_stages)
{
struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
const struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(gfx_state->base.pipeline);
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (dirty_stages & VK_SHADER_STAGE_TASK_BIT_EXT &&
anv_pipeline_has_stage(pipeline, MESA_SHADER_TASK)) {
anv_gfx_has_stage(gfx, MESA_SHADER_TASK)) {
uint64_t push_addr64 =
get_mesh_task_push_addr64(cmd_buffer, pipeline, MESA_SHADER_TASK);
get_mesh_task_push_addr64(cmd_buffer, gfx, MESA_SHADER_TASK);
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_TASK_SHADER_DATA), data) {
data.InlineData[ANV_INLINE_PARAM_PUSH_ADDRESS_OFFSET / 4 + 0] = push_addr64 & 0xffffffff;
@ -631,14 +621,14 @@ cmd_buffer_flush_mesh_inline_data(struct anv_cmd_buffer *cmd_buffer,
}
if (dirty_stages & VK_SHADER_STAGE_MESH_BIT_EXT &&
anv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) {
anv_gfx_has_stage(gfx, MESA_SHADER_MESH)) {
uint64_t push_addr64 =
get_mesh_task_push_addr64(cmd_buffer, pipeline, MESA_SHADER_MESH);
get_mesh_task_push_addr64(cmd_buffer, gfx, MESA_SHADER_MESH);
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_MESH_SHADER_DATA), data) {
data.InlineData[ANV_INLINE_PARAM_PUSH_ADDRESS_OFFSET / 4 + 0] = push_addr64 & 0xffffffff;
data.InlineData[ANV_INLINE_PARAM_PUSH_ADDRESS_OFFSET / 4 + 1] = push_addr64 >> 32;
data.InlineData[ANV_INLINE_PARAM_MESH_PROVOKING_VERTEX / 4] = gfx_state->dyn_state.mesh_provoking_vertex;
data.InlineData[ANV_INLINE_PARAM_MESH_PROVOKING_VERTEX / 4] = gfx->dyn_state.mesh_provoking_vertex;
}
}
@ -752,13 +742,13 @@ ALWAYS_INLINE static void
cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_device *device = cmd_buffer->device;
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(gfx->base.pipeline);
const struct vk_dynamic_graphics_state *dyn =
&cmd_buffer->vk.dynamic_graphics_state;
assert((pipeline->base.base.active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
assert((gfx->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
genX(cmd_buffer_config_l3)(cmd_buffer, device->l3_config);
@ -810,7 +800,7 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
const bool any_dynamic_state_dirty =
vk_dynamic_graphics_state_any_dirty(dyn);
uint32_t descriptors_dirty = cmd_buffer->state.descriptors_dirty &
pipeline->base.base.active_stages;
gfx->active_stages;
descriptors_dirty |=
genX(cmd_buffer_flush_push_descriptors)(cmd_buffer,
@ -919,8 +909,8 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer,
&cmd_buffer->state.gfx.base,
descriptors_dirty,
(const struct anv_shader_bin **)pipeline->base.shaders,
ARRAY_SIZE(pipeline->base.shaders));
(const struct anv_shader_bin **)gfx->shaders,
ARRAY_SIZE(gfx->shaders));
cmd_buffer->state.descriptors_dirty &= ~dirty;
}
@ -928,13 +918,12 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
/* Because we're pushing UBOs, we have to push whenever either
* descriptors or push constants is dirty.
*/
dirty |= cmd_buffer->state.push_constants_dirty &
pipeline->base.base.active_stages;
dirty |= cmd_buffer->state.push_constants_dirty & gfx->active_stages;
#if INTEL_NEEDS_WA_1604061319
/* Testing shows that all the 3DSTATE_CONSTANT_XS need to be emitted if
* any stage has 3DSTATE_CONSTANT_XS emitted.
*/
dirty |= pipeline->base.base.active_stages;
dirty |= gfx->active_stages;
#endif
cmd_buffer_flush_gfx_push_constants(cmd_buffer,
dirty & VK_SHADER_STAGE_ALL_GRAPHICS);
@ -972,8 +961,6 @@ ALWAYS_INLINE static bool
anv_use_generated_draws(const struct anv_cmd_buffer *cmd_buffer, uint32_t count)
{
const struct anv_device *device = cmd_buffer->device;
const struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
/* We cannot generate readable commands in protected mode. */
if (cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT)
@ -983,7 +970,7 @@ anv_use_generated_draws(const struct anv_cmd_buffer *cmd_buffer, uint32_t count)
* simpler for implementing Wa_1306463417, Wa_16011107343.
*/
if ((INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343) &&
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL))
anv_gfx_has_stage(&cmd_buffer->state.gfx, MESA_SHADER_TESS_CTRL))
return false;
return count >= device->physical->instance->generated_indirect_threshold;
@ -1130,14 +1117,13 @@ void genX(CmdDraw)(
uint32_t firstInstance)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (anv_batch_has_error(&cmd_buffer->batch))
return;
const uint32_t count =
vertexCount * instanceCount * pipeline->instance_multiplier;
vertexCount * instanceCount * gfx->instance_multiplier;
anv_measure_snapshot(cmd_buffer,
INTEL_SNAPSHOT_DRAW,
"draw", count);
@ -1151,7 +1137,7 @@ void genX(CmdDraw)(
#if GFX_VER < 11
cmd_buffer_emit_vertex_constants_and_flush(cmd_buffer,
get_vs_prog_data(pipeline),
get_gfx_vs_prog_data(gfx),
firstVertex, firstInstance, 0,
false /* force_flush */);
#endif
@ -1172,7 +1158,7 @@ void genX(CmdDraw)(
prim.VertexCountPerInstance = vertexCount;
prim.StartVertexLocation = firstVertex;
prim.InstanceCount = instanceCount *
pipeline->instance_multiplier;
gfx->instance_multiplier;
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = 0;
#if GFX_VER >= 11
@ -1186,8 +1172,8 @@ void genX(CmdDraw)(
cmd_buffer_post_draw_wa(cmd_buffer, vertexCount, SEQUENTIAL);
trace_intel_end_draw(&cmd_buffer->trace, count,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
void genX(CmdDrawMultiEXT)(
@ -1199,8 +1185,7 @@ void genX(CmdDrawMultiEXT)(
uint32_t stride)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
UNUSED struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@ -1214,12 +1199,12 @@ void genX(CmdDrawMultiEXT)(
#if GFX_VER < 11
vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) {
cmd_buffer_emit_vertex_constants_and_flush(cmd_buffer,
get_vs_prog_data(pipeline),
get_gfx_vs_prog_data(gfx),
draw->firstVertex,
firstInstance, i, !i);
const uint32_t count =
draw->vertexCount * instanceCount * pipeline->instance_multiplier;
draw->vertexCount * instanceCount * gfx->instance_multiplier;
anv_measure_snapshot(cmd_buffer,
INTEL_SNAPSHOT_DRAW,
"draw multi", count);
@ -1232,8 +1217,7 @@ void genX(CmdDrawMultiEXT)(
prim.VertexAccessType = SEQUENTIAL;
prim.VertexCountPerInstance = draw->vertexCount;
prim.StartVertexLocation = draw->firstVertex;
prim.InstanceCount = instanceCount *
pipeline->instance_multiplier;
prim.InstanceCount = instanceCount * gfx->instance_multiplier;
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = 0;
}
@ -1243,8 +1227,8 @@ void genX(CmdDrawMultiEXT)(
SEQUENTIAL);
trace_intel_end_draw_multi(&cmd_buffer->trace, count,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
#else
vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) {
@ -1264,8 +1248,7 @@ void genX(CmdDrawMultiEXT)(
prim.VertexAccessType = SEQUENTIAL;
prim.VertexCountPerInstance = draw->vertexCount;
prim.StartVertexLocation = draw->firstVertex;
prim.InstanceCount = instanceCount *
pipeline->instance_multiplier;
prim.InstanceCount = instanceCount * gfx->instance_multiplier;
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = 0;
prim.ExtendedParametersPresent = true;
@ -1279,8 +1262,8 @@ void genX(CmdDrawMultiEXT)(
SEQUENTIAL);
trace_intel_end_draw_multi(&cmd_buffer->trace, count,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
#endif
}
@ -1294,14 +1277,13 @@ void genX(CmdDrawIndexed)(
uint32_t firstInstance)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (anv_batch_has_error(&cmd_buffer->batch))
return;
const uint32_t count =
indexCount * instanceCount * pipeline->instance_multiplier;
indexCount * instanceCount * gfx->instance_multiplier;
anv_measure_snapshot(cmd_buffer,
INTEL_SNAPSHOT_DRAW,
"draw indexed",
@ -1315,7 +1297,7 @@ void genX(CmdDrawIndexed)(
genX(flush_pipeline_select_3d)(cmd_buffer);
#if GFX_VER < 11
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
cmd_buffer_emit_vertex_constants_and_flush(cmd_buffer, vs_prog_data,
vertexOffset, firstInstance,
0, false /* force_flush */);
@ -1336,8 +1318,7 @@ void genX(CmdDrawIndexed)(
prim.VertexAccessType = RANDOM;
prim.VertexCountPerInstance = indexCount;
prim.StartVertexLocation = firstIndex;
prim.InstanceCount = instanceCount *
pipeline->instance_multiplier;
prim.InstanceCount = instanceCount * gfx->instance_multiplier;
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = vertexOffset;
#if GFX_VER >= 11
@ -1351,8 +1332,8 @@ void genX(CmdDrawIndexed)(
cmd_buffer_post_draw_wa(cmd_buffer, indexCount, RANDOM);
trace_intel_end_draw_indexed(&cmd_buffer->trace, count,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
void genX(CmdDrawMultiIndexedEXT)(
@ -1365,8 +1346,7 @@ void genX(CmdDrawMultiIndexedEXT)(
const int32_t *pVertexOffset)
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@ -1378,7 +1358,7 @@ void genX(CmdDrawMultiIndexedEXT)(
uint32_t i = 0;
#if GFX_VER < 11
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
if (pVertexOffset) {
if (vs_prog_data->uses_drawid) {
bool emitted = true;
@ -1399,7 +1379,7 @@ void genX(CmdDrawMultiIndexedEXT)(
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
const uint32_t count =
draw->indexCount * instanceCount * pipeline->instance_multiplier;
draw->indexCount * instanceCount * gfx->instance_multiplier;
anv_measure_snapshot(cmd_buffer,
INTEL_SNAPSHOT_DRAW,
"draw indexed multi",
@ -1413,8 +1393,7 @@ void genX(CmdDrawMultiIndexedEXT)(
prim.VertexAccessType = RANDOM;
prim.VertexCountPerInstance = draw->indexCount;
prim.StartVertexLocation = draw->firstIndex;
prim.InstanceCount = instanceCount *
pipeline->instance_multiplier;
prim.InstanceCount = instanceCount * gfx->instance_multiplier;
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = *pVertexOffset;
}
@ -1424,8 +1403,8 @@ void genX(CmdDrawMultiIndexedEXT)(
RANDOM);
trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
emitted = false;
}
} else {
@ -1439,7 +1418,7 @@ void genX(CmdDrawMultiIndexedEXT)(
}
vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) {
const uint32_t count =
draw->indexCount * instanceCount * pipeline->instance_multiplier;
draw->indexCount * instanceCount * gfx->instance_multiplier;
anv_measure_snapshot(cmd_buffer,
INTEL_SNAPSHOT_DRAW,
"draw indexed multi",
@ -1453,8 +1432,7 @@ void genX(CmdDrawMultiIndexedEXT)(
prim.VertexAccessType = RANDOM;
prim.VertexCountPerInstance = draw->indexCount;
prim.StartVertexLocation = draw->firstIndex;
prim.InstanceCount = instanceCount *
pipeline->instance_multiplier;
prim.InstanceCount = instanceCount * gfx->instance_multiplier;
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = *pVertexOffset;
}
@ -1464,8 +1442,8 @@ void genX(CmdDrawMultiIndexedEXT)(
RANDOM);
trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
}
} else {
@ -1475,7 +1453,7 @@ void genX(CmdDrawMultiIndexedEXT)(
firstInstance, i, i != 0);
const uint32_t count =
draw->indexCount * instanceCount * pipeline->instance_multiplier;
draw->indexCount * instanceCount * gfx->instance_multiplier;
anv_measure_snapshot(cmd_buffer,
INTEL_SNAPSHOT_DRAW,
"draw indexed multi",
@ -1489,8 +1467,7 @@ void genX(CmdDrawMultiIndexedEXT)(
prim.VertexAccessType = RANDOM;
prim.VertexCountPerInstance = draw->indexCount;
prim.StartVertexLocation = draw->firstIndex;
prim.InstanceCount = instanceCount *
pipeline->instance_multiplier;
prim.InstanceCount = instanceCount * gfx->instance_multiplier;
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = draw->vertexOffset;
}
@ -1500,14 +1477,14 @@ void genX(CmdDrawMultiIndexedEXT)(
RANDOM);
trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
}
#else
vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) {
const uint32_t count =
draw->indexCount * instanceCount * pipeline->instance_multiplier;
draw->indexCount * instanceCount * gfx->instance_multiplier;
anv_measure_snapshot(cmd_buffer,
INTEL_SNAPSHOT_DRAW,
"draw indexed multi",
@ -1524,8 +1501,7 @@ void genX(CmdDrawMultiIndexedEXT)(
prim.VertexAccessType = RANDOM;
prim.VertexCountPerInstance = draw->indexCount;
prim.StartVertexLocation = draw->firstIndex;
prim.InstanceCount = instanceCount *
pipeline->instance_multiplier;
prim.InstanceCount = instanceCount * gfx->instance_multiplier;
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = pVertexOffset ? *pVertexOffset : draw->vertexOffset;
prim.ExtendedParametersPresent = true;
@ -1539,8 +1515,8 @@ void genX(CmdDrawMultiIndexedEXT)(
RANDOM);
trace_intel_end_draw_indexed_multi(&cmd_buffer->trace, count,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
#endif
}
@ -1583,8 +1559,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, counter_buffer, counterBuffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
/* firstVertex is always zero for this draw function */
const uint32_t firstVertex = 0;
@ -1595,7 +1570,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
anv_measure_snapshot(cmd_buffer,
INTEL_SNAPSHOT_DRAW,
"draw indirect byte count",
instanceCount * pipeline->instance_multiplier);
instanceCount * gfx->instance_multiplier);
trace_intel_begin_draw_indirect_byte_count(&cmd_buffer->trace);
/* Select pipeline here to allow
@ -1605,7 +1580,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
genX(flush_pipeline_select_3d)(cmd_buffer);
#if GFX_VER < 11
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
if (vs_prog_data->uses_firstvertex ||
vs_prog_data->uses_baseinstance)
emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
@ -1632,7 +1607,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
mi_store(&b, mi_reg32(GFX7_3DPRIM_START_VERTEX), mi_imm(firstVertex));
mi_store(&b, mi_reg32(GFX7_3DPRIM_INSTANCE_COUNT),
mi_imm(instanceCount * pipeline->instance_multiplier));
mi_imm(instanceCount * gfx->instance_multiplier));
mi_store(&b, mi_reg32(GFX7_3DPRIM_START_INSTANCE), mi_imm(firstInstance));
mi_store(&b, mi_reg32(GFX7_3DPRIM_BASE_VERTEX), mi_imm(0));
@ -1660,9 +1635,9 @@ void genX(CmdDrawIndirectByteCountEXT)(
cmd_buffer_post_draw_wa(cmd_buffer, 1, SEQUENTIAL);
trace_intel_end_draw_indirect_byte_count(&cmd_buffer->trace,
instanceCount * pipeline->instance_multiplier,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
instanceCount * gfx->instance_multiplier,
gfx->vs_source_hash,
gfx->fs_source_hash);
}
static void
@ -1671,8 +1646,7 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
bool indexed,
uint32_t draw_id)
{
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
struct mi_builder b;
mi_builder_init(&b, cmd_buffer->device->info, &cmd_buffer->batch);
@ -1683,9 +1657,9 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
mi_mem32(anv_address_add(addr, 0)));
struct mi_value instance_count = mi_mem32(anv_address_add(addr, 4));
if (pipeline->instance_multiplier > 1) {
if (gfx->instance_multiplier > 1) {
instance_count = mi_imul_imm(&b, instance_count,
pipeline->instance_multiplier);
gfx->instance_multiplier);
}
mi_store(&b, mi_reg32(GFX7_3DPRIM_INSTANCE_COUNT), instance_count);
@ -1728,12 +1702,12 @@ execute_indirect_draw_supported(const struct anv_cmd_buffer *cmd_buffer)
if (!devinfo->has_indirect_unroll)
return false;
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_task_prog_data *task_prog_data = get_task_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
const bool is_multiview = pipeline->instance_multiplier > 1;
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
const struct brw_task_prog_data *task_prog_data = get_gfx_task_prog_data(gfx);
const struct brw_mesh_prog_data *mesh_prog_data = get_gfx_mesh_prog_data(gfx);
const bool is_multiview = gfx->instance_multiplier > 1;
const bool uses_draw_id =
(vs_prog_data && vs_prog_data->uses_drawid) ||
@ -1763,9 +1737,8 @@ emit_indirect_draws(struct anv_cmd_buffer *cmd_buffer,
bool indexed)
{
#if GFX_VER < 11
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
#endif
cmd_buffer_flush_gfx_state(cmd_buffer);
@ -1956,8 +1929,7 @@ void genX(CmdDrawIndirect)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@ -1996,8 +1968,8 @@ void genX(CmdDrawIndirect)(
}
trace_intel_end_draw_indirect(&cmd_buffer->trace, drawCount,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
void genX(CmdDrawIndexedIndirect)(
@ -2009,8 +1981,7 @@ void genX(CmdDrawIndexedIndirect)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@ -2049,8 +2020,8 @@ void genX(CmdDrawIndexedIndirect)(
}
trace_intel_end_draw_indexed_indirect(&cmd_buffer->trace, drawCount,
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
#define MI_PREDICATE_SRC0 0x2400
@ -2144,9 +2115,8 @@ emit_indirect_count_draws(struct anv_cmd_buffer *cmd_buffer,
bool indexed)
{
#if GFX_VER < 11
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
#endif
cmd_buffer_flush_gfx_state(cmd_buffer);
@ -2213,8 +2183,7 @@ void genX(CmdDrawIndirectCount)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@ -2258,8 +2227,8 @@ void genX(CmdDrawIndirectCount)(
trace_intel_end_draw_indirect_count(&cmd_buffer->trace,
anv_address_utrace(count_address),
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
void genX(CmdDrawIndexedIndirectCount)(
@ -2274,8 +2243,7 @@ void genX(CmdDrawIndexedIndirectCount)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@ -2319,8 +2287,8 @@ void genX(CmdDrawIndexedIndirectCount)(
trace_intel_end_draw_indexed_indirect_count(&cmd_buffer->trace,
anv_address_utrace(count_address),
pipeline->vs_source_hash,
pipeline->fs_source_hash);
gfx->vs_source_hash,
gfx->fs_source_hash);
}
void genX(CmdBeginTransformFeedbackEXT)(
@ -2516,10 +2484,9 @@ genX(CmdDrawMeshTasksIndirectEXT)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_task_prog_data *task_prog_data = get_task_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_task_prog_data *task_prog_data = get_gfx_task_prog_data(gfx);
const struct brw_mesh_prog_data *mesh_prog_data = get_gfx_mesh_prog_data(gfx);
struct anv_cmd_state *cmd_state = &cmd_buffer->state;
if (anv_batch_has_error(&cmd_buffer->batch))
@ -2581,10 +2548,9 @@ genX(CmdDrawMeshTasksIndirectCountEXT)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_task_prog_data *task_prog_data = get_task_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_task_prog_data *task_prog_data = get_gfx_task_prog_data(gfx);
const struct brw_mesh_prog_data *mesh_prog_data = get_gfx_mesh_prog_data(gfx);
if (anv_batch_has_error(&cmd_buffer->batch))
return;

36
src/intel/vulkan/genX_cmd_draw_generated_indirect.h
View file

@ -64,9 +64,8 @@ genX(cmd_buffer_emit_generate_draws)(struct anv_cmd_buffer *cmd_buffer,
if (push_data_state.map == NULL)
return ANV_STATE_NULL;
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
const bool use_tbimr = cmd_buffer->state.gfx.dyn_state.use_tbimr;
struct anv_address draw_count_addr;
@ -80,10 +79,10 @@ genX(cmd_buffer_emit_generate_draws)(struct anv_cmd_buffer *cmd_buffer,
const bool wa_16011107343 =
intel_needs_workaround(device->info, 16011107343) &&
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL);
anv_cmd_buffer_has_gfx_stage(cmd_buffer, MESA_SHADER_TESS_CTRL);
const bool wa_22018402687 =
intel_needs_workaround(device->info, 22018402687) &&
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL);
anv_cmd_buffer_has_gfx_stage(cmd_buffer, MESA_SHADER_TESS_EVAL);
const uint32_t wa_insts_size =
((wa_16011107343 ? GENX(3DSTATE_HS_length) : 0) +
@ -97,6 +96,11 @@ genX(cmd_buffer_emit_generate_draws)(struct anv_cmd_buffer *cmd_buffer,
ANV_STATE_NULL;
UNUSED uint32_t wa_insts_offset = 0;
#if INTEL_WA_16011107343_GFX_VER || INTEL_WA_22018402687_GFX_VER
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(gfx->base.pipeline);
#endif
#if INTEL_WA_16011107343_GFX_VER
if (wa_16011107343) {
memcpy(wa_insts_state.map + wa_insts_offset,
@ -145,7 +149,7 @@ genX(cmd_buffer_emit_generate_draws)(struct anv_cmd_buffer *cmd_buffer,
.draw_base = item_base,
.max_draw_count = max_count,
.ring_count = ring_count,
.instance_multiplier = pipeline->instance_multiplier,
.instance_multiplier = gfx->instance_multiplier,
.draw_count = anv_address_is_null(count_addr) ? max_count : 0,
.generated_cmds_addr = anv_address_physical(generated_cmds_addr),
.draw_count_addr = anv_address_physical(draw_count_addr),
@ -212,9 +216,8 @@ genX(cmd_buffer_get_draw_id_addr)(struct anv_cmd_buffer *cmd_buffer,
#if GFX_VER >= 11
return ANV_NULL_ADDRESS;
#else
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
if (!vs_prog_data->uses_drawid)
return ANV_NULL_ADDRESS;
@ -234,9 +237,8 @@ genX(cmd_buffer_get_generated_draw_stride)(struct anv_cmd_buffer *cmd_buffer)
#if GFX_VER >= 11
return 4 * GENX(3DPRIMITIVE_EXTENDED_length);
#else
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
uint32_t len = 0;
@ -303,9 +305,8 @@ genX(cmd_buffer_emit_indirect_generated_draws_inplace)(struct anv_cmd_buffer *cm
device->physical->va.dynamic_state_pool.size);
}
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
if (vs_prog_data->uses_baseinstance ||
vs_prog_data->uses_firstvertex) {
@ -485,9 +486,8 @@ genX(cmd_buffer_emit_indirect_generated_draws_inring)(struct anv_cmd_buffer *cmd
},
cmd_buffer->generation.ring_bo->size);
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
if (vs_prog_data->uses_baseinstance ||
vs_prog_data->uses_firstvertex) {

5
src/intel/vulkan/genX_cmd_draw_helpers.h
View file

@ -106,9 +106,8 @@ update_dirty_vbs_for_gfx8_vb_flush(struct anv_cmd_buffer *cmd_buffer,
#if GFX_VER == 9
const struct vk_dynamic_graphics_state *dyn =
&cmd_buffer->vk.dynamic_graphics_state;
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
const struct brw_vs_prog_data *vs_prog_data = get_gfx_vs_prog_data(gfx);
uint64_t vb_used = dyn->vi->bindings_valid;
if (vs_prog_data->uses_firstvertex ||

168
src/intel/vulkan/genX_gfx_state.c
View file

@ -188,7 +188,8 @@ genX(batch_emit_wa_16014912113)(struct anv_batch *batch,
}
static void
genX(streamout_prologue)(struct anv_cmd_buffer *cmd_buffer)
genX(streamout_prologue)(struct anv_cmd_buffer *cmd_buffer,
const struct anv_cmd_graphics_state *gfx)
{
#if INTEL_WA_16013994831_GFX_VER
/* Wa_16013994831 - Disable preemption during streamout, enable back
@ -197,9 +198,7 @@ genX(streamout_prologue)(struct anv_cmd_buffer *cmd_buffer)
if (!intel_needs_workaround(cmd_buffer->device->info, 16013994831))
return;
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
if (pipeline->uses_xfb) {
if (gfx->uses_xfb) {
genX(cmd_buffer_set_preemption)(cmd_buffer, false);
return;
}
@ -287,6 +286,15 @@ has_ds_feedback_loop(const struct anv_pipeline_bind_map *bind_map,
BITSET_TEST(bind_map->input_attachments, stencil_att));
}
static bool
kill_pixel(const struct brw_wm_prog_data *wm_prog_data,
const struct vk_dynamic_graphics_state *dyn)
{
return wm_prog_data->uses_kill ||
wm_prog_data->uses_omask ||
dyn->ms.alpha_to_coverage_enable;
}
UNUSED static bool
want_stencil_pma_fix(const struct vk_dynamic_graphics_state *dyn,
const struct anv_cmd_graphics_state *gfx,
@ -357,13 +365,11 @@ want_stencil_pma_fix(const struct vk_dynamic_graphics_state *dyn,
assert(d_iview && d_iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
/* 3DSTATE_PS_EXTRA::PixelShaderValid */
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(gfx->base.pipeline);
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
if (gfx->shaders[MESA_SHADER_FRAGMENT] == NULL)
return false;
/* !(3DSTATE_WM::EDSC_Mode == 2) */
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
if (wm_prog_data->early_fragment_tests)
return false;
@ -400,9 +406,9 @@ want_stencil_pma_fix(const struct vk_dynamic_graphics_state *dyn,
* 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
* (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
*/
struct anv_shader_bin *fs_bin = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
struct anv_shader_bin *fs_bin = gfx->shaders[MESA_SHADER_FRAGMENT];
return pipeline->kill_pixel ||
return kill_pixel(wm_prog_data, dyn) ||
has_ds_feedback_loop(&fs_bin->bind_map, dyn) ||
wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
}
@ -437,12 +443,12 @@ anv_line_rasterization_mode(VkLineRasterizationModeKHR line_mode,
* different shader stages which might generate their own type of primitives.
*/
static inline VkPolygonMode
anv_raster_polygon_mode(const struct anv_graphics_pipeline *pipeline,
anv_raster_polygon_mode(const struct anv_cmd_graphics_state *gfx,
VkPolygonMode polygon_mode,
VkPrimitiveTopology primitive_topology)
{
if (anv_pipeline_is_mesh(pipeline)) {
switch (get_mesh_prog_data(pipeline)->primitive_type) {
if (gfx->shaders[MESA_SHADER_MESH] != NULL) {
switch (get_gfx_mesh_prog_data(gfx)->primitive_type) {
case MESA_PRIM_POINTS:
return VK_POLYGON_MODE_POINT;
case MESA_PRIM_LINES:
@ -452,8 +458,8 @@ anv_raster_polygon_mode(const struct anv_graphics_pipeline *pipeline,
default:
UNREACHABLE("invalid primitive type for mesh");
}
} else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
switch (get_gs_prog_data(pipeline)->output_topology) {
} else if (gfx->shaders[MESA_SHADER_GEOMETRY] != NULL) {
switch (get_gfx_gs_prog_data(gfx)->output_topology) {
case _3DPRIM_POINTLIST:
return VK_POLYGON_MODE_POINT;
@ -472,8 +478,8 @@ anv_raster_polygon_mode(const struct anv_graphics_pipeline *pipeline,
return polygon_mode;
}
UNREACHABLE("Unsupported GS output topology");
} else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
switch (get_tes_prog_data(pipeline)->output_topology) {
} else if (gfx->shaders[MESA_SHADER_TESS_EVAL] != NULL) {
switch (get_gfx_tes_prog_data(gfx)->output_topology) {
case INTEL_TESS_OUTPUT_TOPOLOGY_POINT:
return VK_POLYGON_MODE_POINT;
@ -726,8 +732,7 @@ calculate_tile_dimensions(const struct anv_device *device,
#define SET_STAGE(bit, field, value, stage) \
do { \
__typeof(hw_state->field) __v = value; \
if (!anv_pipeline_has_stage(pipeline, \
MESA_SHADER_##stage)) { \
if (gfx->shaders[MESA_SHADER_##stage] == NULL) { \
hw_state->field = __v; \
break; \
} \
@ -772,17 +777,17 @@ calculate_tile_dimensions(const struct anv_device *device,
ALWAYS_INLINE static void
update_urb_config(struct anv_gfx_dynamic_state *hw_state,
const struct anv_graphics_pipeline *pipeline,
const struct anv_cmd_graphics_state *gfx,
const struct anv_device *device)
{
struct intel_urb_config new_cfg = { 0 };
#if GFX_VERx10 >= 125
if (anv_pipeline_is_mesh(pipeline)) {
if (anv_gfx_has_stage(gfx, MESA_SHADER_MESH)) {
const struct brw_task_prog_data *task_prog_data =
get_task_prog_data(pipeline);
get_gfx_task_prog_data(gfx);
const struct brw_mesh_prog_data *mesh_prog_data =
get_mesh_prog_data(pipeline);
get_gfx_mesh_prog_data(gfx);
intel_get_mesh_urb_config(device->info, device->l3_config,
task_prog_data ? task_prog_data->map.size_dw : 0,
mesh_prog_data->map.size / 4, &new_cfg);
@ -790,18 +795,17 @@ update_urb_config(struct anv_gfx_dynamic_state *hw_state,
#endif
{
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
const struct brw_vue_prog_data *prog_data =
!anv_pipeline_has_stage(pipeline, i) ? NULL :
(const struct brw_vue_prog_data *) pipeline->base.shaders[i]->prog_data;
const struct brw_vue_prog_data *prog_data = anv_gfx_has_stage(gfx, i) ?
(const struct brw_vue_prog_data *) gfx->shaders[i]->prog_data :
NULL;
new_cfg.size[i] = prog_data ? prog_data->urb_entry_size : 1;
}
UNUSED bool constrained;
intel_get_urb_config(device->info, device->l3_config,
pipeline->base.base.active_stages &
VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
pipeline->base.base.active_stages & VK_SHADER_STAGE_GEOMETRY_BIT,
anv_gfx_has_stage(gfx, MESA_SHADER_TESS_EVAL),
anv_gfx_has_stage(gfx, MESA_SHADER_GEOMETRY),
&new_cfg, &constrained);
}
@ -819,9 +823,9 @@ update_urb_config(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_fs_msaa_flags(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
if (!wm_prog_data)
return;
@ -832,19 +836,19 @@ update_fs_msaa_flags(struct anv_gfx_dynamic_state *hw_state,
if (!brw_wm_prog_data_is_dynamic(wm_prog_data))
return;
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data = get_gfx_mesh_prog_data(gfx);
enum intel_msaa_flags fs_msaa_flags =
intel_fs_msaa_flags((struct intel_fs_params) {
.shader_sample_shading = wm_prog_data->sample_shading,
.shader_min_sample_shading = pipeline->min_sample_shading,
.state_sample_shading = pipeline->sample_shading_enable,
.shader_min_sample_shading = gfx->min_sample_shading,
.state_sample_shading = gfx->sample_shading_enable,
.rasterization_samples = dyn->ms.rasterization_samples,
.coarse_pixel = !vk_fragment_shading_rate_is_disabled(&dyn->fsr),
.alpha_to_coverage = dyn->ms.alpha_to_coverage_enable,
.provoking_vertex_last = dyn->rs.provoking_vertex == VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT,
.first_vue_slot = pipeline->first_vue_slot,
.primitive_id_index = pipeline->primitive_id_index,
.first_vue_slot = gfx->first_vue_slot,
.primitive_id_index = gfx->primitive_id_index,
.per_primitive_remapping = mesh_prog_data &&
mesh_prog_data->map.wa_18019110168_active,
});
@ -856,9 +860,9 @@ ALWAYS_INLINE static void
update_ps(struct anv_gfx_dynamic_state *hw_state,
const struct anv_device *device,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
if (!wm_prog_data) {
#if GFX_VER < 20
@ -872,8 +876,7 @@ update_ps(struct anv_gfx_dynamic_state *hw_state,
return;
}
const struct anv_shader_bin *fs_bin =
pipeline->base.shaders[MESA_SHADER_FRAGMENT];
const struct anv_shader_bin *fs_bin = gfx->shaders[MESA_SHADER_FRAGMENT];
struct GENX(3DSTATE_PS) ps = {};
intel_set_ps_dispatch_state(&ps, device->info, wm_prog_data,
MAX2(dyn->ms.rasterization_samples, 1),
@ -922,9 +925,9 @@ update_ps(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_ps_extra_wm(struct anv_gfx_dynamic_state *hw_state,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
if (!wm_prog_data)
return;
@ -950,10 +953,9 @@ update_ps_extra_wm(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_ps_extra_has_uav(struct anv_gfx_dynamic_state *hw_state,
const struct anv_cmd_graphics_state *gfx,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
/* Force fragment shader execution if occlusion queries are active to
* ensure PS_DEPTH_COUNT is correct. Otherwise a fragment shader with
@ -970,11 +972,10 @@ update_ps_extra_has_uav(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_ps_extra_kills_pixel(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_cmd_graphics_state *gfx,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
struct anv_shader_bin *fs_bin = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
struct anv_shader_bin *fs_bin = gfx->shaders[MESA_SHADER_FRAGMENT];
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
SET_STAGE(PS_EXTRA, ps_extra.PixelShaderKillsPixel,
wm_prog_data &&
@ -995,8 +996,7 @@ update_vfg_list_cut_index(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_streamout(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_cmd_graphics_state *gfx,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
SET(STREAMOUT, so.RenderingDisable, dyn->rs.rasterizer_discard_enable);
SET(STREAMOUT, so.RenderStreamSelect, dyn->rs.rasterization_stream);
@ -1039,10 +1039,10 @@ update_streamout(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_provoking_vertex(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
#if GFX_VERx10 >= 200
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
/* In order to respect the table indicated by Vulkan 1.4.312,
* 28.9. Barycentric Interpolation, we need to program the provoking
@ -1087,10 +1087,10 @@ update_provoking_vertex(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_topology(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
uint32_t topology =
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL) ?
gfx->shaders[MESA_SHADER_TESS_EVAL] != NULL ?
_3DPRIM_PATCHLIST(dyn->ts.patch_control_points) :
vk_to_intel_primitive_type[dyn->ia.primitive_topology];
@ -1101,8 +1101,7 @@ update_topology(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_cps(struct anv_gfx_dynamic_state *hw_state,
const struct anv_device *device,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_graphics_pipeline *pipeline)
const struct vk_dynamic_graphics_state *dyn)
{
#if GFX_VER >= 30
SET(COARSE_PIXEL, coarse_pixel.CPSizeX,
@ -1128,11 +1127,11 @@ update_cps(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_te(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
const struct brw_tes_prog_data *tes_prog_data = get_gfx_tes_prog_data(gfx);
if (tes_prog_data && anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
if (tes_prog_data) {
if (dyn->ts.domain_origin == VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT) {
SET(TE, te.OutputTopology, tes_prog_data->output_topology);
} else {
@ -1221,8 +1220,7 @@ update_clip_max_viewport(struct anv_gfx_dynamic_state *hw_state,
ALWAYS_INLINE static void
update_clip_raster(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_cmd_graphics_state *gfx,
const struct anv_graphics_pipeline *pipeline)
const struct anv_cmd_graphics_state *gfx)
{
/* Take dynamic primitive topology in to account with
* 3DSTATE_RASTER::APIMode
@ -1237,7 +1235,7 @@ update_clip_raster(struct anv_gfx_dynamic_state *hw_state,
dyn->ms.rasterization_samples);
const VkPolygonMode dynamic_raster_mode =
anv_raster_polygon_mode(pipeline,
anv_raster_polygon_mode(gfx,
dyn->rs.polygon_mode,
dyn->ia.primitive_topology);
@ -1289,7 +1287,7 @@ update_clip_raster(struct anv_gfx_dynamic_state *hw_state,
VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT);
#if GFX_VERx10 >= 200
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
SET(RASTER, raster.LegacyBaryAssignmentDisable,
wm_prog_data && wm_prog_data->vertex_attributes_bypass);
#endif
@ -1966,15 +1964,15 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_PROVOKING_VERTEX) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_FSR))
update_fs_msaa_flags(hw_state, dyn, pipeline);
update_fs_msaa_flags(hw_state, dyn, gfx);
if (gfx->dirty & ANV_CMD_DIRTY_PRERASTER_SHADERS)
update_urb_config(hw_state, pipeline, device);
update_urb_config(hw_state, gfx, device);
if ((gfx->dirty & ANV_CMD_DIRTY_PS) ||
BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_FS_MSAA_FLAGS)) {
update_ps(hw_state, device, dyn, pipeline);
update_ps_extra_wm(hw_state, pipeline);
update_ps(hw_state, device, dyn, gfx);
update_ps_extra_wm(hw_state, gfx);
}
if (gfx->dirty &
@ -1984,16 +1982,16 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
(ANV_CMD_DIRTY_PS | ANV_CMD_DIRTY_OCCLUSION_QUERY_ACTIVE)
#endif
)
update_ps_extra_has_uav(hw_state, gfx, pipeline);
update_ps_extra_has_uav(hw_state, gfx);
if ((gfx->dirty & ANV_CMD_DIRTY_PS) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE))
update_ps_extra_kills_pixel(hw_state, dyn, gfx, pipeline);
update_ps_extra_kills_pixel(hw_state, dyn, gfx);
if ((gfx->dirty & ANV_CMD_DIRTY_OCCLUSION_QUERY_ACTIVE) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_RASTERIZER_DISCARD_ENABLE) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_RASTERIZATION_STREAM))
update_streamout(hw_state, dyn, gfx, pipeline);
update_streamout(hw_state, dyn, gfx);
if (
#if GFX_VERx10 >= 200
@ -2001,11 +1999,11 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
(gfx->dirty & ANV_CMD_DIRTY_PS) ||
#endif
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_PROVOKING_VERTEX))
update_provoking_vertex(hw_state, dyn, pipeline);
update_provoking_vertex(hw_state, dyn, gfx);
if ((gfx->dirty & ANV_CMD_DIRTY_DS) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY))
update_topology(hw_state, dyn, pipeline);
update_topology(hw_state, dyn, gfx);
if ((gfx->dirty & ANV_CMD_DIRTY_VS) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_VI) ||
@ -2016,12 +2014,12 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
#if GFX_VER >= 11
if (device->vk.enabled_extensions.KHR_fragment_shading_rate &&
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_FSR))
update_cps(hw_state, device, dyn, pipeline);
update_cps(hw_state, device, dyn);
#endif /* GFX_VER >= 11 */
if ((gfx->dirty & ANV_CMD_DIRTY_DS) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_DOMAIN_ORIGIN))
update_te(hw_state, dyn, pipeline);
update_te(hw_state, dyn, gfx);
if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_LINE_WIDTH))
update_line_width(hw_state, dyn);
@ -2048,7 +2046,7 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_CLIP_ENABLE) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_CLAMP_ENABLE) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_CONSERVATIVE_MODE))
update_clip_raster(hw_state, dyn, gfx, pipeline);
update_clip_raster(hw_state, dyn, gfx);
if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES))
update_multisample(hw_state, dyn);
@ -2109,7 +2107,7 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_WRITE_MASKS) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_BLEND_ENABLES) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_BLEND_EQUATIONS)) {
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
update_blend_state(hw_state, dyn, gfx, device,
wm_prog_data != NULL,
wm_prog_data != NULL ?
@ -2141,7 +2139,7 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
if (intel_needs_workaround(device->info, 14018283232) &&
((gfx->dirty & ANV_CMD_DIRTY_PS) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE))) {
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
SET(WA_14018283232, wa_14018283232_toggle,
dyn->ds.depth.bounds_test.enable &&
wm_prog_data &&
@ -2153,14 +2151,14 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
* the pipeline change or the dynamic value change, check the value and
* reemit if needed.
*/
const struct brw_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline);
const struct brw_tcs_prog_data *tcs_prog_data = get_gfx_tcs_prog_data(gfx);
if (tcs_prog_data && tcs_prog_data->input_vertices == 0 &&
((gfx->dirty & ANV_CMD_DIRTY_HS) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_PATCH_CONTROL_POINTS)))
SET(TCS_INPUT_VERTICES, tcs_input_vertices, dyn->ts.patch_control_points);
#if INTEL_WA_18019110168_GFX_VER
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data = get_gfx_mesh_prog_data(gfx);
const bool mesh_provoking_vertex_update =
intel_needs_workaround(device->info, 18019110168) &&
mesh_prog_data &&
@ -2382,14 +2380,14 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
#if INTEL_WA_16011107343_GFX_VER
/* Will be emitted in front of every draw instead */
if (intel_needs_workaround(device->info, 16011107343) &&
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL))
anv_cmd_buffer_has_gfx_stage(cmd_buffer, MESA_SHADER_TESS_CTRL))
BITSET_CLEAR(hw_state->dirty, ANV_GFX_STATE_HS);
#endif
#if INTEL_WA_22018402687_GFX_VER
/* Will be emitted in front of every draw instead */
if (intel_needs_workaround(device->info, 22018402687) &&
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
anv_cmd_buffer_has_gfx_stage(cmd_buffer, MESA_SHADER_TESS_EVAL))
BITSET_CLEAR(hw_state->dirty, ANV_GFX_STATE_DS);
#endif
@ -2411,7 +2409,7 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_FS_MSAA_FLAGS)) {
push_consts->gfx.fs_msaa_flags = hw_state->fs_msaa_flags;
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data = get_gfx_mesh_prog_data(gfx);
if (mesh_prog_data) {
push_consts->gfx.fs_per_prim_remap_offset =
pipeline->base.shaders[MESA_SHADER_MESH]->kernel.offset +
@ -2630,7 +2628,7 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
}
if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_STREAMOUT)) {
genX(streamout_prologue)(cmd_buffer);
genX(streamout_prologue)(cmd_buffer, gfx);
anv_batch_emit_merge(&cmd_buffer->batch, GENX(3DSTATE_STREAMOUT),
pipeline, partial.so, so) {
@ -3171,7 +3169,7 @@ genX(cmd_buffer_flush_gfx_hw_state)(struct anv_cmd_buffer *cmd_buffer)
}
#if INTEL_WA_18038825448_GFX_VER
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
if (wm_prog_data) {
genX(cmd_buffer_set_coarse_pixel_active)(
cmd_buffer,

86
src/intel/vulkan/genX_pipeline.c
View file

@ -175,7 +175,8 @@ emit_ves_vf_instancing(struct anv_batch *batch,
bool emit_in_pipeline)
{
const struct anv_device *device = pipeline->base.base.device;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_vs_prog_data *vs_prog_data =
get_pipeline_vs_prog_data(pipeline);
const uint64_t inputs_read = vs_prog_data->inputs_read;
const uint64_t double_inputs_read =
vs_prog_data->double_inputs_read & inputs_read;
@ -325,7 +326,7 @@ emit_vertex_input(struct anv_graphics_pipeline *pipeline,
pipeline, vi, true /* emit_in_pipeline */);
}
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_vs_prog_data *vs_prog_data = get_pipeline_vs_prog_data(pipeline);
const bool needs_svgs_elem = pipeline->svgs_count > 1 ||
!vs_prog_data->uses_drawid;
const uint32_t id_slot = pipeline->vs_input_elements;
@ -448,13 +449,14 @@ emit_vertex_input(struct anv_graphics_pipeline *pipeline,
static bool
sbe_primitive_id_override(struct anv_graphics_pipeline *pipeline)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data =
get_pipeline_wm_prog_data(pipeline);
if (!wm_prog_data)
return false;
if (anv_pipeline_is_mesh(pipeline)) {
const struct brw_mesh_prog_data *mesh_prog_data =
get_mesh_prog_data(pipeline);
get_pipeline_mesh_prog_data(pipeline);
const struct brw_mue_map *mue = &mesh_prog_data->map;
return (wm_prog_data->inputs & VARYING_BIT_PRIMITIVE_ID) &&
mue->per_primitive_offsets[VARYING_SLOT_PRIMITIVE_ID] == -1;
@ -470,9 +472,9 @@ sbe_primitive_id_override(struct anv_graphics_pipeline *pipeline)
static void
emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_pipeline_wm_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data =
get_mesh_prog_data(pipeline);
get_pipeline_mesh_prog_data(pipeline);
UNUSED const struct anv_device *device = pipeline->base.base.device;
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
@ -487,7 +489,7 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline)
const struct intel_vue_map *vue_map =
anv_pipeline_is_mesh(pipeline) ?
&get_mesh_prog_data(pipeline)->map.vue_map :
&get_pipeline_mesh_prog_data(pipeline)->map.vue_map :
&anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
anv_pipeline_emit(pipeline, final.sbe, GENX(3DSTATE_SBE), sbe) {
@ -619,18 +621,11 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline)
sf.VertexSubPixelPrecisionSelect = _8Bit;
sf.AALineDistanceMode = true;
bool point_from_shader;
if (anv_pipeline_is_primitive(pipeline)) {
const struct brw_vue_prog_data *last_vue_prog_data =
anv_pipeline_get_last_vue_prog_data(pipeline);
point_from_shader = last_vue_prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ;
} else {
assert(anv_pipeline_is_mesh(pipeline));
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
point_from_shader = mesh_prog_data->map.vue_map.slots_valid & VARYING_BIT_PSIZ;
}
if (point_from_shader) {
const struct intel_vue_map *vue_map =
anv_pipeline_is_primitive(pipeline) ?
&anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map :
&get_pipeline_mesh_prog_data(pipeline)->map.vue_map;
if (vue_map->slots_valid & VARYING_BIT_PSIZ) {
sf.PointWidthSource = Vertex;
} else {
sf.PointWidthSource = State;
@ -645,7 +640,8 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
const struct vk_viewport_state *vp,
const struct vk_rasterization_state *rs)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data =
get_pipeline_wm_prog_data(pipeline);
(void) wm_prog_data;
anv_pipeline_emit(pipeline, partial.clip, GENX(3DSTATE_CLIP), clip) {
@ -675,7 +671,8 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
!(last->vue_map.slots_valid & VARYING_BIT_LAYER);
} else if (anv_pipeline_is_mesh(pipeline)) {
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data =
get_pipeline_mesh_prog_data(pipeline);
clip.ForceZeroRTAIndexEnable =
mesh_prog_data->map.per_primitive_offsets[VARYING_SLOT_LAYER] < 0;
@ -693,7 +690,8 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
if (!anv_pipeline_is_mesh(pipeline))
continue;
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data =
get_pipeline_mesh_prog_data(pipeline);
clip_mesh.PrimitiveHeaderEnable = mesh_prog_data->map.has_per_primitive_header;
clip_mesh.UserClipDistanceClipTestEnableBitmask = mesh_prog_data->clip_distance_mask;
clip_mesh.UserClipDistanceCullTestEnableBitmask = mesh_prog_data->cull_distance_mask;
@ -907,7 +905,8 @@ static void
emit_3dstate_vs(struct anv_graphics_pipeline *pipeline)
{
const struct intel_device_info *devinfo = pipeline->base.base.device->info;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_vs_prog_data *vs_prog_data =
get_pipeline_vs_prog_data(pipeline);
const struct anv_shader_bin *vs_bin =
pipeline->base.shaders[MESA_SHADER_VERTEX];
@ -1020,8 +1019,10 @@ emit_3dstate_hs_ds(struct anv_graphics_pipeline *pipeline,
const struct anv_shader_bin *tes_bin =
pipeline->base.shaders[MESA_SHADER_TESS_EVAL];
const struct brw_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline);
const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
const struct brw_tcs_prog_data *tcs_prog_data =
get_pipeline_tcs_prog_data(pipeline);
const struct brw_tes_prog_data *tes_prog_data =
get_pipeline_tes_prog_data(pipeline);
uint32_t hs_dwords[GENX(3DSTATE_HS_length)];
anv_pipeline_emit_tmp(pipeline, hs_dwords, GENX(3DSTATE_HS), hs) {
@ -1164,13 +1165,13 @@ geom_or_tess_prim_id_used(struct anv_graphics_pipeline *pipeline)
{
const struct brw_tcs_prog_data *tcs_prog_data =
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL) ?
get_tcs_prog_data(pipeline) : NULL;
get_pipeline_tcs_prog_data(pipeline) : NULL;
const struct brw_tes_prog_data *tes_prog_data =
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL) ?
get_tes_prog_data(pipeline) : NULL;
get_pipeline_tes_prog_data(pipeline) : NULL;
const struct brw_gs_prog_data *gs_prog_data =
anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) ?
get_gs_prog_data(pipeline) : NULL;
get_pipeline_gs_prog_data(pipeline) : NULL;
return (tcs_prog_data && tcs_prog_data->include_primitive_id) ||
(tes_prog_data && tes_prog_data->include_primitive_id) ||
@ -1183,7 +1184,7 @@ emit_3dstate_te(struct anv_graphics_pipeline *pipeline)
anv_pipeline_emit(pipeline, partial.te, GENX(3DSTATE_TE), te) {
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
const struct brw_tes_prog_data *tes_prog_data =
get_tes_prog_data(pipeline);
get_pipeline_tes_prog_data(pipeline);
te.Partitioning = tes_prog_data->partitioning;
te.TEDomain = tes_prog_data->domain;
@ -1245,7 +1246,8 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline)
const struct intel_device_info *devinfo = pipeline->base.base.device->info;
const struct anv_shader_bin *gs_bin =
pipeline->base.shaders[MESA_SHADER_GEOMETRY];
const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
const struct brw_gs_prog_data *gs_prog_data =
get_pipeline_gs_prog_data(pipeline);
uint32_t gs_dwords[GENX(3DSTATE_GS_length)];
anv_pipeline_emit_tmp(pipeline, gs_dwords, GENX(3DSTATE_GS), gs) {
@ -1324,7 +1326,8 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
const struct vk_color_blend_state *cb,
const struct vk_render_pass_state *rp)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data =
get_pipeline_wm_prog_data(pipeline);
anv_pipeline_emit(pipeline, partial.wm, GENX(3DSTATE_WM), wm) {
wm.StatisticsEnable = true;
@ -1360,7 +1363,8 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
return;
}
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data =
get_pipeline_wm_prog_data(pipeline);
uint32_t ps_dwords[GENX(3DSTATE_PS_length)];
anv_pipeline_emit_tmp(pipeline, ps_dwords, GENX(3DSTATE_PS), ps) {
@ -1421,7 +1425,8 @@ emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
const struct vk_rasterization_state *rs,
const struct vk_graphics_pipeline_state *state)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data =
get_pipeline_wm_prog_data(pipeline);
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
anv_pipeline_emit(pipeline, partial.ps_extra, GENX(3DSTATE_PS_EXTRA), ps);
@ -1479,7 +1484,8 @@ compute_kill_pixel(struct anv_graphics_pipeline *pipeline,
return;
}
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data =
get_pipeline_wm_prog_data(pipeline);
/* This computes the KillPixel portion of the computation for whether or
* not we want to enable the PMA fix on gfx8 or gfx9. It's given by this
@ -1581,7 +1587,8 @@ emit_task_state(struct anv_graphics_pipeline *pipeline)
}
const struct intel_device_info *devinfo = pipeline->base.base.device->info;
const struct brw_task_prog_data *task_prog_data = get_task_prog_data(pipeline);
const struct brw_task_prog_data *task_prog_data =
get_pipeline_task_prog_data(pipeline);
const struct intel_cs_dispatch_info task_dispatch =
brw_cs_get_dispatch_info(devinfo, &task_prog_data->base, NULL);
@ -1631,7 +1638,8 @@ emit_mesh_state(struct anv_graphics_pipeline *pipeline)
assert(anv_pipeline_is_mesh(pipeline));
const struct anv_shader_bin *mesh_bin = pipeline->base.shaders[MESA_SHADER_MESH];
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data =
get_pipeline_mesh_prog_data(pipeline);
uint32_t mesh_control_dwords[GENX(3DSTATE_MESH_CONTROL_length)];
anv_pipeline_emit_tmp(pipeline, mesh_control_dwords, GENX(3DSTATE_MESH_CONTROL), mc) {
@ -1849,7 +1857,8 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
void
genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
{
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
const struct brw_cs_prog_data *prog_data =
(const struct brw_cs_prog_data *)pipeline->cs->prog_data;
const struct intel_device_info *devinfo = pipeline->base.device->info;
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, prog_data, NULL);
@ -1907,7 +1916,8 @@ genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
{
struct anv_device *device = pipeline->base.device;
const struct intel_device_info *devinfo = device->info;
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct brw_cs_prog_data *cs_prog_data =
(struct brw_cs_prog_data *) pipeline->cs->prog_data;
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);