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freedreno: remove all clover support code

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Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34051>
This commit is contained in:
Karol Herbst 2025-03-13 16:50:44 +01:00 • committed by Marge Bot
parent d073701a24
commit 8963defa4f
12 changed files with 9 additions and 134 deletions
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38
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -1348,41 +1348,6 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
}
}
/* Load a kernel param: src[] = { address }. */
static void
emit_intrinsic_load_kernel_input(struct ir3_context *ctx,
nir_intrinsic_instr *intr,
struct ir3_instruction **dst)
{
const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
struct ir3_builder *b = &ctx->build;
unsigned offset = nir_intrinsic_base(intr);
unsigned p = ir3_const_reg(const_state, IR3_CONST_ALLOC_KERNEL_PARAMS, 0);
struct ir3_instruction *src0 = ir3_get_src(ctx, &intr->src[0])[0];
if (is_same_type_mov(src0) && (src0->srcs[0]->flags & IR3_REG_IMMED)) {
offset += src0->srcs[0]->iim_val;
/* kernel param position is in bytes, but constant space is 32b registers: */
compile_assert(ctx, !(offset & 0x3));
dst[0] = create_uniform(b, p + (offset / 4));
} else {
/* kernel param position is in bytes, but constant space is 32b registers: */
compile_assert(ctx, !(offset & 0x3));
/* TODO we should probably be lowering this in nir, and also handling
* non-32b inputs.. Also we probably don't want to be using
* SP_MODE_CONTROL.CONSTANT_DEMOTION_ENABLE for KERNEL shaders..
*/
src0 = ir3_SHR_B(b, src0, 0, create_immed(b, 2), 0);
dst[0] = create_uniform_indirect(b, offset / 4, TYPE_U32,
ir3_get_addr0(ctx, src0, 1));
}
}
/* src[] = { block_index } */
static void
emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
@ -2878,9 +2843,6 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
case nir_intrinsic_load_input:
setup_input(ctx, intr);
break;
case nir_intrinsic_load_kernel_input:
emit_intrinsic_load_kernel_input(ctx, intr, dst);
break;
/* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
* pass and replaced by an ir3-specifc version that adds the
* dword-offset in the last source.

6
src/freedreno/ir3/ir3_nir.c
View file

@ -1545,12 +1545,6 @@ ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
align(const_state->image_dims.count, 4) / 4, 1);
}
if (v->type == MESA_SHADER_KERNEL && v->cs.req_input_mem) {
ir3_const_reserve_space(&const_state->allocs,
IR3_CONST_ALLOC_KERNEL_PARAMS,
align(v->cs.req_input_mem, 4) / 4, 1);
}
if ((v->type == MESA_SHADER_VERTEX) && (compiler->gen < 5) &&
v->stream_output.num_outputs > 0) {
ir3_const_reserve_space(&const_state->allocs, IR3_CONST_ALLOC_TFBO,

3
src/freedreno/ir3/ir3_shader.c
View file

@ -359,7 +359,6 @@ alloc_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
case MESA_SHADER_COMPUTE:
case MESA_SHADER_KERNEL:
v->cs.req_input_mem = shader->cs.req_input_mem;
v->cs.req_local_mem = shader->cs.req_local_mem;
break;
@ -810,8 +809,6 @@ ir3_const_alloc_type_to_string(enum ir3_const_alloc_type type)
return "ubo_ptrs";
case IR3_CONST_ALLOC_IMAGE_DIMS:
return "image_dims";
case IR3_CONST_ALLOC_KERNEL_PARAMS:
return "kernel_params";
case IR3_CONST_ALLOC_TFBO:
return "tfbo";
case IR3_CONST_ALLOC_PRIMITIVE_PARAM:

12
src/freedreno/ir3/ir3_shader.h
View file

@ -210,20 +210,18 @@ enum ir3_const_alloc_type {
* for images that have image_{load,store,size,atomic*} intrinsics.
*/
IR3_CONST_ALLOC_IMAGE_DIMS = 8,
/* OpenCL */
IR3_CONST_ALLOC_KERNEL_PARAMS = 9,
/* OpenGL, TFBO addresses only for vs on a3xx/a4xx */
IR3_CONST_ALLOC_TFBO = 10,
IR3_CONST_ALLOC_TFBO = 9,
/* Common, stage-dependent primitive params:
* vs, gs: uvec4(primitive_stride, vertex_stride, 0, 0)
* hs, ds: uvec4(primitive_stride, vertex_stride,
* patch_stride, patch_vertices_in)
* uvec4(tess_param_base, tess_factor_base)
*/
IR3_CONST_ALLOC_PRIMITIVE_PARAM = 11,
IR3_CONST_ALLOC_PRIMITIVE_PARAM = 10,
/* Common, mapping from varying location to offset. */
IR3_CONST_ALLOC_PRIMITIVE_MAP = 12,
IR3_CONST_ALLOC_MAX = 13,
IR3_CONST_ALLOC_PRIMITIVE_MAP = 11,
IR3_CONST_ALLOC_MAX = 12,
};
struct ir3_const_allocation {
@ -932,7 +930,6 @@ struct ir3_shader_variant {
bool fbfetch_coherent : 1;
} fs;
struct {
unsigned req_input_mem;
unsigned req_local_mem;
bool force_linear_dispatch;
uint32_t local_invocation_id;
@ -1009,7 +1006,6 @@ struct ir3_shader {
union {
/* for compute shaders: */
struct {
unsigned req_input_mem; /* in dwords */
unsigned req_local_mem;
bool force_linear_dispatch;
} cs;

5
src/gallium/drivers/freedreno/a5xx/fd5_screen.c
View file

@ -64,12 +64,11 @@ fd5_screen_is_format_supported(struct pipe_screen *pscreen,
if ((usage &
(PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_COMPUTE_RESOURCE)) &&
PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) &&
(fd5_pipe2color(format) != RB5_NONE) &&
(fd5_pipe2tex(format) != TFMT5_NONE)) {
retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT | PIPE_BIND_SHARED |
PIPE_BIND_COMPUTE_RESOURCE);
PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
}
if (usage & PIPE_BIND_SHADER_IMAGE) {

2
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
View file

@ -212,7 +212,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
if (ctx->gen_dirty & BIT(FD6_GROUP_CONST))
fd6_emit_cs_user_consts<CHIP>(ctx, ring, cs);
if (cs->v->need_driver_params || info->input)
if (cs->v->need_driver_params)
fd6_emit_cs_driver_params<CHIP>(ctx, ring, cs, info);
OUT_PKT7(ring, CP_SET_MARKER, 1);

5
src/gallium/drivers/freedreno/a6xx/fd6_const.cc
View file

@ -484,11 +484,6 @@ fd6_emit_cs_driver_params(struct fd_context *ctx,
struct fd6_compute_state *cs,
const struct pipe_grid_info *info)
{
/* info->input not handled in the UBO path. I believe this was only
* ever used by clover
*/
assert(!info->input);
if (CHIP == A7XX && ctx->screen->info->a7xx.load_shader_consts_via_preamble) {
const struct ir3_const_state *const_state = ir3_const_state(cs->v);
struct ir3_driver_params_cs compute_params =

5
src/gallium/drivers/freedreno/a6xx/fd6_screen.cc
View file

@ -87,11 +87,10 @@ fd6_screen_is_format_supported(struct pipe_screen *pscreen,
if ((usage &
(PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_COMPUTE_RESOURCE)) &&
PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) &&
has_color && has_tex) {
retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT | PIPE_BIND_SHARED |
PIPE_BIND_COMPUTE_RESOURCE);
PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
}
/* For ARB_framebuffer_no_attachments: */

2
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -319,8 +319,6 @@ fd_init_compute_caps(struct fd_screen *screen)
caps->address_bits = screen->gen >= 5 ? 64 : 32;
snprintf(caps->ir_target, sizeof(caps->ir_target), "ir3");
caps->grid_dimension = 3;
caps->max_grid_size[0] =

33
src/gallium/drivers/freedreno/freedreno_state.c
View file

@ -717,38 +717,6 @@ fd_bind_compute_state(struct pipe_context *pctx, void *state) in_dt
fd_context_dirty_shader(ctx, PIPE_SHADER_COMPUTE, FD_DIRTY_SHADER_PROG);
}
/* TODO pipe_context::set_compute_resources() should DIAF and clover
* should be updated to use pipe_context::set_constant_buffer() and
* pipe_context::set_shader_images(). Until then just directly frob
* the UBO/image state to avoid the rest of the driver needing to
* know about this bastard api..
*/
static void
fd_set_compute_resources(struct pipe_context *pctx, unsigned start,
unsigned count, struct pipe_surface **prscs) in_dt
{
struct fd_context *ctx = fd_context(pctx);
struct fd_constbuf_stateobj *so = &ctx->constbuf[PIPE_SHADER_COMPUTE];
for (unsigned i = 0; i < count; i++) {
const uint32_t index = i + start + 1; /* UBOs start at index 1 */
if (!prscs) {
util_copy_constant_buffer(&so->cb[index], NULL, false);
so->enabled_mask &= ~(1 << index);
} else if (prscs[i]->format == PIPE_FORMAT_NONE) {
struct pipe_constant_buffer cb = {
.buffer = prscs[i]->texture,
};
util_copy_constant_buffer(&so->cb[index], &cb, false);
so->enabled_mask |= (1 << index);
} else {
// TODO images
unreachable("finishme");
}
}
}
/* used by clover to bind global objects, returning the bo address
* via handles[n]
*/
@ -833,7 +801,6 @@ fd_state_init(struct pipe_context *pctx)
if (has_compute(fd_screen(pctx->screen))) {
pctx->bind_compute_state = fd_bind_compute_state;
pctx->set_compute_resources = fd_set_compute_resources;
pctx->set_global_binding = fd_set_global_binding;
}

20
src/gallium/drivers/freedreno/ir3/ir3_const.h
View file

@ -426,24 +426,6 @@ emit_common_consts(const struct ir3_shader_variant *v,
}
}
/* emit kernel params */
static inline void
emit_kernel_params(struct fd_context *ctx, const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring, const struct pipe_grid_info *info)
assert_dt
{
const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset =
const_state->allocs.consts[IR3_CONST_ALLOC_KERNEL_PARAMS].offset_vec4;
if (ir3_const_can_upload(&const_state->allocs, IR3_CONST_ALLOC_KERNEL_PARAMS,
v->constlen)) {
ring_wfi(ctx->batch, ring);
emit_const_user(ring, v, offset * 4,
align(v->cs.req_input_mem, 4),
(uint32_t *)info->input);
}
}
static inline struct ir3_driver_params_vs
ir3_build_driver_params_vs(struct fd_context *ctx,
const struct pipe_draw_info *info,
@ -634,8 +616,6 @@ ir3_emit_cs_driver_params(const struct ir3_shader_variant *v,
const struct pipe_grid_info *info)
assert_dt
{
emit_kernel_params(ctx, v, ring, info);
/* a3xx/a4xx can inject these directly */
if (ctx->screen->gen <= 4)
return;

12
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
View file

@ -265,17 +265,6 @@ ir3_shader_compute_state_create(struct pipe_context *pctx,
{
struct fd_context *ctx = fd_context(pctx);
/* req_input_mem will only be non-zero for cl kernels (ie. clover).
* This isn't a perfect test because I guess it is possible (but
* uncommon) for none for the kernel parameters to be a global,
* but ctx->set_global_bindings() can't fail, so this is the next
* best place to fail if we need a newer version of kernel driver:
*/
if ((cso->req_input_mem > 0) &&
fd_device_version(ctx->dev) < FD_VERSION_BO_IOVA) {
return NULL;
}
enum ir3_wavesize_option api_wavesize = IR3_SINGLE_OR_DOUBLE;
enum ir3_wavesize_option real_wavesize = IR3_SINGLE_OR_DOUBLE;
@ -311,7 +300,6 @@ ir3_shader_compute_state_create(struct pipe_context *pctx,
struct ir3_shader *shader =
ir3_shader_from_nir(compiler, nir, &ir3_options, NULL);
shader->cs.req_input_mem = align(cso->req_input_mem, 4) / 4; /* byte->dword */
shader->cs.req_local_mem = cso->static_shared_mem;
struct ir3_shader_state *hwcso = calloc(1, sizeof(*hwcso));