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amd: rename enums ARCTURUS -> MI100, ALDEBARAN -> MI200

Browse source 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19477>
This commit is contained in:
Marek Olšák 2022-11-02 14:42:40 -04:00
parent bdfacd0a24
commit 8956682810
12 changed files with 34 additions and 34 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
src/amd/common/ac_gpu_info.c
View file

@ -38,11 +38,11 @@
#include <stdio.h>
#include <ctype.h>
#define AMDGPU_ARCTURUS_RANGE 0x32, 0x3C
#define AMDGPU_ALDEBARAN_RANGE 0x3C, 0xFF
#define AMDGPU_MI100_RANGE 0x32, 0x3C
#define AMDGPU_MI200_RANGE 0x3C, 0xFF
#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
#define ASICREV_IS_ALDEBARAN(r) ASICREV_IS(r, ALDEBARAN)
#define ASICREV_IS_MI100(r) ASICREV_IS(r, MI100)
#define ASICREV_IS_MI200(r) ASICREV_IS(r, MI200)
#ifdef _WIN32
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
@ -799,8 +799,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
identify_chip(VEGA10);
identify_chip(VEGA12);
identify_chip(VEGA20);
identify_chip(ARCTURUS);
identify_chip(ALDEBARAN);
identify_chip(MI100);
identify_chip(MI200);
break;
case FAMILY_RV:
identify_chip(RAVEN);
@ -955,7 +955,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
info->num_tcc_blocks /= 2;
}
} else {
if (!info->has_graphics && info->family >= CHIP_ALDEBARAN)
if (!info->has_graphics && info->family >= CHIP_MI200)
info->tcc_cache_line_size = 128;
else
info->tcc_cache_line_size = 64;
@ -1064,7 +1064,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
*/
info->has_accelerated_dot_product =
info->family == CHIP_VEGA20 ||
(info->family >= CHIP_ARCTURUS && info->family != CHIP_NAVI10);
(info->family >= CHIP_MI100 && info->family != CHIP_NAVI10);
/* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
info->has_load_ctx_reg_pkt =
@ -1137,11 +1137,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
if (info->gfx_level >= GFX11) {
assert(info->max_sa_per_se <= 2);
info->cu_mask[i][j] = device_info.cu_bitmap[i % 4][(i / 4) * 2 + j];
} else if (info->family == CHIP_ARCTURUS) {
} else if (info->family == CHIP_MI100) {
/* The CU bitmap in amd gpu info structure is
* 4x4 size array, and it's usually suitable for Vega
* ASICs which has 4*2 SE/SA layout.
* But for Arcturus, SE/SA layout is changed to 8*1.
* But for MI100, SE/SA layout is changed to 8*1.
* To mostly reduce the impact, we make it compatible
* with current bitmap array as below:
* SE4 --> cu_bitmap[0][1]
@ -1280,7 +1280,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
info->sgpr_alloc_granularity = 8;
}
info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_ARCTURUS;
info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_MI100;
info->never_stop_sq_perf_counters = info->gfx_level == GFX10 ||
info->gfx_level == GFX10_3;
info->never_send_perfcounter_stop = info->gfx_level == GFX11;
@ -1296,7 +1296,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104;
if (!info->has_graphics && info->family >= CHIP_ALDEBARAN) {
if (!info->has_graphics && info->family >= CHIP_MI200) {
info->min_wave64_vgpr_alloc = 8;
info->max_vgpr_alloc = 512;
info->wave64_vgpr_alloc_granularity = 8;

2
src/amd/common/ac_rtld.c
View file

@ -454,7 +454,7 @@ bool ac_rtld_open(struct ac_rtld_binary *binary, struct ac_rtld_open_info i)
*/
unsigned prefetch_distance = 0;
if (!i.info->has_graphics && i.info->family >= CHIP_ALDEBARAN)
if (!i.info->has_graphics && i.info->family >= CHIP_MI200)
prefetch_distance = 16;
else if (i.info->gfx_level >= GFX10)
prefetch_distance = 3;

8
src/amd/common/amd_family.c
View file

@ -78,10 +78,10 @@ const char *ac_get_family_name(enum radeon_family family)
return "RAVEN2";
case CHIP_RENOIR:
return "RENOIR";
case CHIP_ARCTURUS:
return "ARCTURUS";
case CHIP_ALDEBARAN:
return "ALDEBARAN";
case CHIP_MI100:
return "MI100";
case CHIP_MI200:
return "MI200";
case CHIP_NAVI10:
return "NAVI10";
case CHIP_NAVI12:

4
src/amd/common/amd_family.h
View file

@ -114,8 +114,8 @@ enum radeon_family
CHIP_RAVEN, /* Ryzen 2000, 3000 */
CHIP_RAVEN2, /* Ryzen 2200U, 3200U */
CHIP_RENOIR, /* Ryzen 4000, 5000 */
CHIP_ARCTURUS, /* MI100 */
CHIP_ALDEBARAN, /* MI200 */
CHIP_MI100,
CHIP_MI200,
/* GFX10.1 (RDNA 1) */
CHIP_NAVI10, /* Radeon 5600, 5700 */
CHIP_NAVI12, /* Radeon Pro 5600M */

4
src/amd/compiler/aco_ir.cpp
View file

@ -158,7 +158,7 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
default: break;
}
program->dev.sram_ecc_enabled = program->family == CHIP_ARCTURUS;
program->dev.sram_ecc_enabled = program->family == CHIP_MI100;
/* apparently gfx702 also has fast v_fma_f32 but I can't find a family for that */
program->dev.has_fast_fma32 = program->gfx_level >= GFX9;
if (program->family == CHIP_TAHITI || program->family == CHIP_CARRIZO ||
@ -168,7 +168,7 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
program->dev.fused_mad_mix = program->gfx_level >= GFX10;
if (program->family == CHIP_VEGA12 || program->family == CHIP_VEGA20 ||
program->family == CHIP_ARCTURUS || program->family == CHIP_ALDEBARAN)
program->family == CHIP_MI100 || program->family == CHIP_MI200)
program->dev.fused_mad_mix = true;
if (program->gfx_level >= GFX11) {

4
src/amd/llvm/ac_llvm_util.c
View file

@ -153,9 +153,9 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
case CHIP_RAVEN2:
case CHIP_RENOIR:
return "gfx909";
case CHIP_ARCTURUS:
case CHIP_MI100:
return "gfx908";
case CHIP_ALDEBARAN:
case CHIP_MI200:
return "gfx90a";
case CHIP_NAVI10:
return "gfx1010";

2
src/amd/llvm/ac_nir_to_llvm.c
View file

@ -1614,7 +1614,7 @@ static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx, const nir_te
break;
}
/* Aldebaran doesn't have image_sample_lz, but image_sample behaves like lz. */
/* MI200 doesn't have image_sample_lz, but image_sample behaves like lz. */
if (!ctx->ac.has_3d_cube_border_color_mipmap)
args->level_zero = false;

4
src/amd/vulkan/winsys/null/radv_null_winsys.c
View file

@ -60,7 +60,7 @@ static const struct {
[CHIP_VEGA20] = {0x66A0, 16, true},
[CHIP_RAVEN] = {0x15DD, 2, false},
[CHIP_RENOIR] = {0x1636, 2, false},
[CHIP_ARCTURUS] = {0x738C, 2, true},
[CHIP_MI100] = {0x738C, 2, true},
[CHIP_NAVI10] = {0x7310, 16, true},
[CHIP_NAVI12] = {0x7360, 8, true},
[CHIP_NAVI14] = {0x7340, 8, true},
@ -148,7 +148,7 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
info->has_accelerated_dot_product =
info->family == CHIP_VEGA20 ||
(info->family >= CHIP_ARCTURUS && info->family != CHIP_NAVI10);
(info->family >= CHIP_MI100 && info->family != CHIP_NAVI10);
info->address32_hi = info->gfx_level >= GFX9 ? 0xffff8000u : 0x0;

6
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
View file

@ -2793,7 +2793,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
if (dec->stream_type == RDECODE_CODEC_JPEG) {
if (sctx->family == CHIP_ARCTURUS || sctx->family == CHIP_ALDEBARAN)
if (sctx->family == CHIP_MI100 || sctx->family == CHIP_MI200)
dec->njctx = 2;
else
dec->njctx = 1;
@ -2913,8 +2913,8 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
dec->jpg.direct_reg = true;
break;
case CHIP_ARCTURUS:
case CHIP_ALDEBARAN:
case CHIP_MI100:
case CHIP_MI200:
case CHIP_NAVI21:
case CHIP_NAVI22:
case CHIP_NAVI23:

4
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -418,7 +418,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
}
/* Set the pointer to border colors. */
/* Aldebaran doesn't support border colors. */
/* MI200 doesn't support border colors. */
if (sctx->border_color_buffer) {
uint64_t bc_va = sctx->border_color_buffer->gpu_address;
@ -437,7 +437,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
sctx->gfx_level >= GFX10 ? 0x20 : 0);
}
if (!info->has_graphics && info->family >= CHIP_ARCTURUS) {
if (!info->has_graphics && info->family >= CHIP_MI100) {
radeon_set_sh_reg_seq(R_00B894_COMPUTE_STATIC_THREAD_MGMT_SE4, 4);
radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));

4
src/gallium/drivers/radeonsi/si_get.c
View file

@ -854,8 +854,8 @@ static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_for
/* JPEG supports YUV400 and YUV444 */
if (profile == PIPE_VIDEO_PROFILE_JPEG_BASELINE) {
if (sscreen->info.family >= CHIP_NAVI21 || sscreen->info.family == CHIP_ARCTURUS ||
sscreen->info.family == CHIP_ALDEBARAN)
if (sscreen->info.family >= CHIP_NAVI21 || sscreen->info.family == CHIP_MI100 ||
sscreen->info.family == CHIP_MI200)
return (format == PIPE_FORMAT_NV12 || format == PIPE_FORMAT_Y8_400_UNORM ||
format == PIPE_FORMAT_Y8_U8_V8_444_UNORM || format == PIPE_FORMAT_YUYV);
else

2
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -790,7 +790,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader)
/* Hardware VGPRs. */
/* Thread IDs are packed in VGPR0, 10 bits per component or stored in 3 separate VGPRs */
if (ctx->screen->info.gfx_level >= GFX11 ||
(!ctx->screen->info.has_graphics && ctx->screen->info.family >= CHIP_ALDEBARAN))
(!ctx->screen->info.has_graphics && ctx->screen->info.family >= CHIP_MI200))
ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.local_invocation_ids);
else
ac_add_arg(&ctx->args, AC_ARG_VGPR, 3, AC_ARG_INT, &ctx->args.local_invocation_ids);