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ir3/delay: Fix full->half and half->full delay

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The current compiler never does this, but the new compiler will start to
in mergeregs mode. There is an extra penalty for this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
This commit is contained in:
Connor Abbott 2021-02-22 15:00:55 +01:00 • committed by Emma Anholt
parent 9ad83f51eb
commit 890de1a436
1 changed files with 18 additions and 5 deletions
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19
src/freedreno/ir3/ir3_delay.c
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@ -88,12 +88,25 @@ ir3_delayslots(struct ir3_instruction *assigner,
if (is_flow(consumer) || is_sfu(consumer) || is_tex(consumer) ||
is_mem(consumer)) {
return 6;
} else if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) &&
} else {
/* assigner and consumer are both alu */
assert(n > 0);
/* In mergedregs mode, there is an extra 2-cycle penalty when half of
* a full-reg is read as a half-reg or when a half-reg is read as a
* full-reg.
*/
bool mismatched_half =
(assigner->regs[0]->flags & IR3_REG_HALF) !=
(consumer->regs[n - 1]->flags & IR3_REG_HALF);
unsigned penalty = mismatched_half ? 2 : 0;
if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) &&
(n == 3)) {
/* special case, 3rd src to cat3 not required on first cycle */
return 1;
return 1 + penalty;
} else {
return 3;
return 3 + penalty;
}
}
}