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pvr: Fix descriptor set address calculation
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com> Acked-by: Frank Binns <frank.binns@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>
This commit is contained in:
Simon Perretta
Marge Bot
parent
5287edd6d2
commit
88e42e18d9
3 changed files with 107 additions and 62 deletions
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@ -311,6 +311,11 @@ mesa_stage_to_pvr(gl_shader_stage mesa_stage)
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unreachable("Unsupported gl_shader_stage.");
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}
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static bool descriptor_is_dynamic(VkDescriptorType type)
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{
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return (type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
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type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC);
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}
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static void
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trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b,
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@ -325,12 +330,9 @@ trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b,
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struct pvr_pipeline_layout *pipeline_layout =
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b->shader->ctx->pipeline_layout;
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/* Defaults for offline compiler. */
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/* TODO: Load these from an offline pipeline description
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* if using the offline compiler.
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*/
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unsigned desc_set_table_sh_reg = 0;
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unsigned flat_desc_idx = binding;
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unsigned desc_set_table_sh_reg;
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unsigned desc_set_offset;
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unsigned desc_offset;
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if (pipeline_layout) {
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/* Fetch shared registers containing descriptor set table address. */
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@ -341,26 +343,45 @@ trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b,
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pipeline_layout->sh_reg_layout_per_stage[pvr_stage]
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.descriptor_set_addrs_table.offset;
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/* Lookup offsets for descriptor set and descriptor. */
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/* Calculate offset for the descriptor set. */
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assert(desc_set < pipeline_layout->set_count);
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desc_set_offset = desc_set * sizeof(pvr_dev_addr_t); /* Table is an array
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of addresses. */
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unsigned binding_count =
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pipeline_layout->set_layout[desc_set]->binding_count;
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assert(binding < binding_count);
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const struct pvr_descriptor_set_layout *set_layout =
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pipeline_layout->set_layout[desc_set];
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const struct pvr_descriptor_set_layout_mem_layout *mem_layout =
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&set_layout->memory_layout_in_dwords_per_stage[pvr_stage];
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flat_desc_idx = ~0U;
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for (unsigned u = 0; u < binding_count; ++u) {
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unsigned binding_number =
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pipeline_layout->set_layout[desc_set]->bindings[u].binding_number;
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/* Calculate offset for the descriptor/binding. */
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assert(binding < set_layout->binding_count);
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if (binding_number == binding) {
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flat_desc_idx = pipeline_layout->set_layout[desc_set]
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->bindings[u]
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.descriptor_index;
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break;
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}
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}
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assert(flat_desc_idx != ~0U);
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const struct pvr_descriptor_set_layout_binding *binding_layout =
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pvr_get_descriptor_binding(set_layout, binding);
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assert(binding_layout);
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/* TODO: Handle secondaries. */
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/* TODO: Handle bindings having multiple descriptors
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* (VkDescriptorSetLayoutBinding->descriptorCount).
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*/
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if (descriptor_is_dynamic(binding_layout->type))
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desc_offset = set_layout->total_size_in_dwords;
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else
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desc_offset = mem_layout->primary_offset;
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desc_offset +=
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binding_layout->per_stage_offset_in_dwords[pvr_stage].primary;
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desc_offset *= sizeof(uint32_t); /* DWORDs to bytes. */
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} else {
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/* Dummy defaults for offline compiler. */
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/* TODO: Load these from an offline pipeline description
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* if using the offline compiler.
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*/
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desc_set_table_sh_reg = 0;
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desc_set_offset = desc_set * sizeof(pvr_dev_addr_t);
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desc_offset = binding * sizeof(pvr_dev_addr_t);
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}
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unsigned desc_set_table_addr_idx = b->shader->ctx->next_ssa_idx++;
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@ -384,8 +405,6 @@ trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b,
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->instr;
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rogue_add_instr_comment(instr, "desc_set_table_addr_hi");
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/* TODO: Don't add offsets if the descriptor set/flat descriptor is 0. */
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/* Offset the descriptor set table address to access the descriptor set. */
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unsigned desc_set_table_addr_offset_idx = b->shader->ctx->next_ssa_idx++;
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rogue_regarray *desc_set_table_addr_offset_64 =
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@ -395,14 +414,27 @@ trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b,
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rogue_ssa_vec_regarray(b->shader, 1, desc_set_table_addr_offset_idx, 1),
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};
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unsigned desc_set_table_addr_offset_lo_idx = b->shader->ctx->next_ssa_idx++;
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unsigned desc_set_table_addr_offset_hi_idx = b->shader->ctx->next_ssa_idx++;
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rogue_reg *desc_set_table_addr_offset_lo =
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rogue_ssa_reg(b->shader, desc_set_table_addr_offset_lo_idx);
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rogue_reg *desc_set_table_addr_offset_hi =
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rogue_ssa_reg(b->shader, desc_set_table_addr_offset_hi_idx);
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rogue_MOV(b,
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rogue_ref_reg(desc_set_table_addr_offset_lo),
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rogue_ref_imm(desc_set_offset));
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rogue_MOV(b, rogue_ref_reg(desc_set_table_addr_offset_hi), rogue_ref_imm(0));
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rogue_ADD64(b,
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rogue_ref_regarray(desc_set_table_addr_offset_2x32[0]),
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rogue_ref_regarray(desc_set_table_addr_offset_2x32[1]),
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rogue_ref_io(ROGUE_IO_NONE),
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rogue_ref_regarray(desc_set_table_addr_2x32[0]),
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rogue_ref_regarray(desc_set_table_addr_2x32[1]),
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rogue_ref_imm(desc_set * 4), /* TODO: use UMADD64 instead */
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rogue_ref_imm(0),
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rogue_ref_reg(desc_set_table_addr_offset_lo),
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rogue_ref_reg(desc_set_table_addr_offset_hi),
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rogue_ref_io(ROGUE_IO_NONE));
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unsigned desc_set_addr_idx = b->shader->ctx->next_ssa_idx++;
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@ -429,14 +461,27 @@ trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b,
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rogue_ssa_vec_regarray(b->shader, 1, desc_addr_offset_idx, 1),
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};
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unsigned desc_addr_offset_lo_idx = b->shader->ctx->next_ssa_idx++;
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unsigned desc_addr_offset_hi_idx = b->shader->ctx->next_ssa_idx++;
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rogue_reg *desc_addr_offset_val_lo =
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rogue_ssa_reg(b->shader, desc_addr_offset_lo_idx);
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rogue_reg *desc_addr_offset_val_hi =
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rogue_ssa_reg(b->shader, desc_addr_offset_hi_idx);
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rogue_MOV(b,
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rogue_ref_reg(desc_addr_offset_val_lo),
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rogue_ref_imm(desc_offset));
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rogue_MOV(b, rogue_ref_reg(desc_addr_offset_val_hi), rogue_ref_imm(0));
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rogue_ADD64(b,
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rogue_ref_regarray(desc_addr_offset_2x32[0]),
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rogue_ref_regarray(desc_addr_offset_2x32[1]),
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rogue_ref_io(ROGUE_IO_NONE),
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rogue_ref_regarray(desc_set_addr_2x32[0]),
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rogue_ref_regarray(desc_set_addr_2x32[1]),
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rogue_ref_imm(flat_desc_idx * 4), /* TODO: use UMADD64 instead */
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rogue_ref_imm(0),
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rogue_ref_reg(desc_addr_offset_val_lo),
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rogue_ref_reg(desc_addr_offset_val_hi),
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rogue_ref_io(ROGUE_IO_NONE));
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unsigned desc_addr_idx = intr->dest.ssa.index;
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@ -407,4 +407,38 @@ struct pvr_pipeline_layout {
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} per_stage_reg_info[PVR_STAGE_ALLOCATION_COUNT];
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};
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static int pvr_compare_layout_binding(const void *a, const void *b)
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{
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uint32_t binding_a;
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uint32_t binding_b;
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binding_a = ((struct pvr_descriptor_set_layout_binding *)a)->binding_number;
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binding_b = ((struct pvr_descriptor_set_layout_binding *)b)->binding_number;
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if (binding_a < binding_b)
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return -1;
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if (binding_a > binding_b)
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return 1;
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return 0;
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}
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/* This function does not assume that the binding will always exist for a
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* particular binding_num. Caller should check before using the return pointer.
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*/
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static struct pvr_descriptor_set_layout_binding *
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pvr_get_descriptor_binding(const struct pvr_descriptor_set_layout *layout,
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const uint32_t binding_num)
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{
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struct pvr_descriptor_set_layout_binding binding;
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binding.binding_number = binding_num;
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return bsearch(&binding,
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layout->bindings,
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layout->binding_count,
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sizeof(binding),
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pvr_compare_layout_binding);
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}
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#endif /* PVR_COMMON_H */
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@ -1339,40 +1339,6 @@ VkResult pvr_FreeDescriptorSets(VkDevice _device,
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return VK_SUCCESS;
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}
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static int pvr_compare_layout_binding(const void *a, const void *b)
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{
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uint32_t binding_a;
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uint32_t binding_b;
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binding_a = ((struct pvr_descriptor_set_layout_binding *)a)->binding_number;
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binding_b = ((struct pvr_descriptor_set_layout_binding *)b)->binding_number;
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if (binding_a < binding_b)
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return -1;
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if (binding_a > binding_b)
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return 1;
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return 0;
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}
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/* This function does not assume that the binding will always exist for a
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* particular binding_num. Caller should check before using the return pointer.
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*/
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static struct pvr_descriptor_set_layout_binding *
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pvr_get_descriptor_binding(const struct pvr_descriptor_set_layout *layout,
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const uint32_t binding_num)
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{
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struct pvr_descriptor_set_layout_binding binding;
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binding.binding_number = binding_num;
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return bsearch(&binding,
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layout->bindings,
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layout->binding_count,
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sizeof(binding),
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pvr_compare_layout_binding);
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}
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static void pvr_descriptor_update_buffer_info(
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const struct pvr_device *device,
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const VkWriteDescriptorSet *write_set,
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