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radv: move the optimized context reg macros with other similar ones
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34145>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
30948e63f4
commit
88df7e709a
1 changed files with 58 additions and 58 deletions
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@ -56,64 +56,6 @@ radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned
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#define radeon_set_context_reg_idx(cs, reg, idx, value) \
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radeon_set_reg(cs, reg, idx, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
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/* Packet building helpers for SH registers. */
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#define radeon_set_sh_reg_seq(cs, reg, num) radeon_set_reg_seq(cs, reg, num, 0, SI_SH, PKT3_SET_SH_REG, 0)
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#define radeon_set_sh_reg(cs, reg, value) radeon_set_reg(cs, reg, 0, value, SI_SH, PKT3_SET_SH_REG)
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#define radeon_set_sh_reg_idx(info, cs, reg, idx, value) \
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do { \
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assert((idx)); \
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unsigned __opcode = PKT3_SET_SH_REG_INDEX; \
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if ((info)->gfx_level < GFX10) \
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__opcode = PKT3_SET_SH_REG; \
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radeon_set_reg(cs, reg, idx, value, SI_SH, __opcode); \
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} while (0)
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/* Packet building helpers for UCONFIG registers. */
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#define radeon_set_uconfig_reg_seq(cs, reg, num) \
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radeon_set_reg_seq(cs, reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, 0)
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#define radeon_set_uconfig_reg(cs, reg, value) radeon_set_reg(cs, reg, 0, value, CIK_UCONFIG, PKT3_SET_UCONFIG_REG)
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#define radeon_set_uconfig_reg_idx(info, cs, reg, idx, value) \
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do { \
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assert((idx)); \
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unsigned __opcode = PKT3_SET_UCONFIG_REG_INDEX; \
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if ((info)->gfx_level < GFX9 || ((info)->gfx_level == GFX9 && (info)->me_fw_version < 26)) \
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__opcode = PKT3_SET_UCONFIG_REG; \
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radeon_set_reg(cs, reg, idx, value, CIK_UCONFIG, __opcode); \
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} while (0)
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/*
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* On GFX10, there is a bug with the ME implementation of its content addressable memory (CAM),
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* that means that it can skip register writes due to not taking correctly into account the
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* fields from the GRBM_GFX_INDEX. With this bit we can force the write.
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*/
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#define radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg, num) \
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do { \
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const bool __filter_cam_workaround = (gfx_level) >= GFX10 && (qf) == RADV_QUEUE_GENERAL; \
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radeon_set_reg_seq(cs, reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, __filter_cam_workaround); \
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} while (0)
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#define radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, reg, value) \
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do { \
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radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg, 1); \
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radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_privileged_config_reg(cs, reg, value) \
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do { \
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assert((reg) < CIK_UCONFIG_REG_OFFSET); \
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assert((cs)->cdw + 6 <= (cs)->reserved_dw); \
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radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); \
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radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_PERF)); \
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radeon_emit(cs, value); \
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radeon_emit(cs, 0); /* unused */ \
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radeon_emit(cs, (reg) >> 2); \
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radeon_emit(cs, 0); /* unused */ \
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} while (0)
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#define radeon_opt_set_context_reg(cmdbuf, reg, reg_enum, value) \
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do { \
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struct radv_cmd_buffer *__cmdbuf = (cmdbuf); \
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@ -198,6 +140,64 @@ radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned
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} \
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} while (0)
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/* Packet building helpers for SH registers. */
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#define radeon_set_sh_reg_seq(cs, reg, num) radeon_set_reg_seq(cs, reg, num, 0, SI_SH, PKT3_SET_SH_REG, 0)
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#define radeon_set_sh_reg(cs, reg, value) radeon_set_reg(cs, reg, 0, value, SI_SH, PKT3_SET_SH_REG)
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#define radeon_set_sh_reg_idx(info, cs, reg, idx, value) \
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do { \
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assert((idx)); \
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unsigned __opcode = PKT3_SET_SH_REG_INDEX; \
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if ((info)->gfx_level < GFX10) \
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__opcode = PKT3_SET_SH_REG; \
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radeon_set_reg(cs, reg, idx, value, SI_SH, __opcode); \
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} while (0)
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/* Packet building helpers for UCONFIG registers. */
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#define radeon_set_uconfig_reg_seq(cs, reg, num) \
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radeon_set_reg_seq(cs, reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, 0)
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#define radeon_set_uconfig_reg(cs, reg, value) radeon_set_reg(cs, reg, 0, value, CIK_UCONFIG, PKT3_SET_UCONFIG_REG)
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#define radeon_set_uconfig_reg_idx(info, cs, reg, idx, value) \
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do { \
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assert((idx)); \
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unsigned __opcode = PKT3_SET_UCONFIG_REG_INDEX; \
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if ((info)->gfx_level < GFX9 || ((info)->gfx_level == GFX9 && (info)->me_fw_version < 26)) \
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__opcode = PKT3_SET_UCONFIG_REG; \
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radeon_set_reg(cs, reg, idx, value, CIK_UCONFIG, __opcode); \
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} while (0)
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/*
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* On GFX10, there is a bug with the ME implementation of its content addressable memory (CAM),
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* that means that it can skip register writes due to not taking correctly into account the
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* fields from the GRBM_GFX_INDEX. With this bit we can force the write.
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*/
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#define radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg, num) \
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do { \
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const bool __filter_cam_workaround = (gfx_level) >= GFX10 && (qf) == RADV_QUEUE_GENERAL; \
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radeon_set_reg_seq(cs, reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, __filter_cam_workaround); \
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} while (0)
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#define radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, reg, value) \
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do { \
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radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg, 1); \
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radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_privileged_config_reg(cs, reg, value) \
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do { \
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assert((reg) < CIK_UCONFIG_REG_OFFSET); \
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assert((cs)->cdw + 6 <= (cs)->reserved_dw); \
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radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); \
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radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_PERF)); \
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radeon_emit(cs, value); \
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radeon_emit(cs, 0); /* unused */ \
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radeon_emit(cs, (reg) >> 2); \
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radeon_emit(cs, 0); /* unused */ \
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} while (0)
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ALWAYS_INLINE static void
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radv_cp_wait_mem(struct radeon_cmdbuf *cs, const enum radv_queue_family qf, const uint32_t op, const uint64_t va,
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const uint32_t ref, const uint32_t mask)
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