diff --git a/src/freedreno/registers/a2xx.xml b/src/freedreno/registers/a2xx.xml
index 1b0bf44bd3d..2c7388d9fcd 100644
--- a/src/freedreno/registers/a2xx.xml
+++ b/src/freedreno/registers/a2xx.xml
@@ -1387,6 +1387,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x2357" name="A225_GRAS_UCP5W"/>
 	<reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/>
 	<reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/>
+	<reg32 offset="0x2381" name="PA_SU_POLY_OFFSET_FRONT_OFFSET"/>
+	<reg32 offset="0x2382" name="PA_SU_POLY_OFFSET_BACK_SCALE"/>
 	<reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/>
 	<reg32 offset="0x4000" name="SQ_CONSTANT_0"/>
 	<reg32 offset="0x4800" name="SQ_FETCH_0"/>
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
index 38286ec939b..32da74f85a5 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
@@ -301,6 +301,18 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
 		OUT_RING(ring, fui(1.0));                /* PA_CL_GB_VERT_DISC_ADJ */
 		OUT_RING(ring, fui(1.0));                /* PA_CL_GB_HORZ_CLIP_ADJ */
 		OUT_RING(ring, fui(1.0));                /* PA_CL_GB_HORZ_DISC_ADJ */
+
+		if (rasterizer->base.offset_tri) {
+			/* TODO: why multiply scale by 2 ? without it deqp test fails
+			 * deqp/piglit tests aren't very precise
+			 */
+			OUT_PKT3(ring, CP_SET_CONSTANT, 5);
+			OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE));
+			OUT_RING(ring, fui(rasterizer->base.offset_scale * 2.0f)); /* FRONT_SCALE */
+			OUT_RING(ring, fui(rasterizer->base.offset_units));        /* FRONT_OFFSET */
+			OUT_RING(ring, fui(rasterizer->base.offset_scale * 2.0f)); /* BACK_SCALE */
+			OUT_RING(ring, fui(rasterizer->base.offset_units));        /* BACK_OFFSET */
+		}
 	}
 
 	/* NOTE: scissor enabled bit is part of rasterizer state: */