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freedreno/a5xx,a6xx: rename MSAA_ENABLE to LINE_MODE in GRAS_SU_CNTL
This bit seems like the control for line mode of rastrization. That can be simply figured out by comparing dEQP-VK.rasterization.primitives.no_stipple.bresenham_lines, dEQP-VK.rasterization.primitives.no_stipple.rectangular_lines and dEQP-VK.rasterization.primitives.no_stipple.lines. For opengl, the value of bresenham lines mode, which is 0, is set by default and the value of rectangular mode, which is 0x1, is set when multi-sampled. For vulkan, the bresenham lines are enabled when lineRasterizationMode is VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT, which sets the bit to 0, while the value is 1 when it's VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT, that seems to be default. If both multi-sampled and bresenham-lines are used when primitive type is line, the bit is to be set as 0 and makes msaa disabled. Note that this is only tested on a6xx, but I guess it's likely the same for a5xx. Signed-off-by: Hyunjun Ko <zzoon@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
This commit is contained in:
parent
d729038c07
commit
88afceacf0
10 changed files with 25 additions and 14 deletions
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@ -5382,7 +5382,7 @@ clusters:
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00000000 GRAS_CL_Z_CLAMP[0xe].MAX: 0.000000
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00000000 GRAS_CL_Z_CLAMP[0xf].MIN: 0.000000
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00000000 GRAS_CL_Z_CLAMP[0xf].MAX: 0.000000
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00000010 GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 }
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00000010 GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
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00000000 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
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00000000 GRAS_SU_POINT_SIZE: 0.000000
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00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
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@ -5627,7 +5627,7 @@ clusters:
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00000000 GRAS_CL_Z_CLAMP[0xe].MAX: 0.000000
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00000000 GRAS_CL_Z_CLAMP[0xf].MIN: 0.000000
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00000000 GRAS_CL_Z_CLAMP[0xf].MAX: 0.000000
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00000010 GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 }
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00000010 GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
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00000000 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
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00000000 GRAS_SU_POINT_SIZE: 0.000000
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00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
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@ -1214,7 +1214,7 @@ t4 write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
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enable_mask: 0x7
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0000000001054730: 0000: 40809001 00000814
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t4 write GRAS_SU_CNTL (8090)
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GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET }
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GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET | LINE_MODE = BRESENHAM }
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0000000001054730: 0000: 40809001 00000814
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group_id: 22
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count: 4
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@ -1323,7 +1323,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
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!+ 3f800000 GRAS_CL_VPORT[0].ZSCALE: 1.000000
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+ 00000000 GRAS_CL_Z_CLAMP[0].MIN: 0.000000
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!+ 3f800000 GRAS_CL_Z_CLAMP[0].MAX: 1.000000
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!+ 00000814 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET }
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!+ 00000814 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET | LINE_MODE = BRESENHAM }
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!+ ffc00001 GRAS_SU_POINT_MINMAX: { MIN = 0.062500 | MAX = 4092.000000 }
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!+ 00000010 GRAS_SU_POINT_SIZE: 1.000000
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+ 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
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@ -819,7 +819,7 @@ t4 write GRAS_CL_CNTL (8000)
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GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
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0000000001123000: 0000: 40800002 00000080 00000000
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t4 write GRAS_SU_CNTL (8090)
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GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 }
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GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
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000000000112300c: 0000: 40809001 00000014
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t4 write GRAS_SU_POINT_MINMAX (8091)
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GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
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@ -930,7 +930,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
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!+ 44340000 GRAS_CL_VPORT[0].YSCALE: 720.000000
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!+ 3f000000 GRAS_CL_VPORT[0].ZOFFSET: 0.500000
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!+ 3f000000 GRAS_CL_VPORT[0].ZSCALE: 0.500000
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!+ 00000014 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 }
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!+ 00000014 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
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!+ 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
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!+ 00000010 GRAS_SU_POINT_SIZE: 1.000000
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+ 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
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@ -5060,7 +5060,7 @@ t4 write GRAS_CL_CNTL (8000)
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GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
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0000000001123000: 0000: 40800002 00000080 00000000
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t4 write GRAS_SU_CNTL (8090)
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GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 }
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GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
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000000000112300c: 0000: 40809001 00000014
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t4 write GRAS_SU_POINT_MINMAX (8091)
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GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
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@ -5181,7 +5181,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
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+ 44340000 GRAS_CL_VPORT[0].YSCALE: 720.000000
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+ 3f000000 GRAS_CL_VPORT[0].ZOFFSET: 0.500000
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+ 3f000000 GRAS_CL_VPORT[0].ZSCALE: 0.500000
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+ 00000014 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 }
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+ 00000014 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
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+ 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
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+ 00000010 GRAS_SU_POINT_SIZE: 1.000000
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+ 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
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@ -1846,7 +1846,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<bitfield name="FRONT_CW" pos="2" type="boolean"/>
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<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
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<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
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<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
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<bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
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<!-- probably LINEHALFWIDTH is the same as a4xx.. -->
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</reg32>
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<reg32 offset="0xe091" name="GRAS_SU_POINT_MINMAX">
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@ -1597,7 +1597,7 @@ to upconvert to 32b float internally?
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<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
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<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
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<bitfield name="UNK12" pos="12"/>
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<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
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<bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
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<bitfield name="UNK15" low="15" high="16"/>
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<!--
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This is set by the blob when multiview is enabled, but doesn't seem
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@ -366,5 +366,14 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<value name="ADDR_64B" value="1"/>
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</enum>
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<doc>
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Line mode for a5xx+
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Note that Bresenham lines are only supported with MSAA disabled.
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</doc>
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<enum name="a5xx_line_mode">
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<value value="0x0" name="BRESENHAM"/>
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<value value="0x1" name="RECTANGULAR"/>
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</enum>
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</database>
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@ -1990,7 +1990,7 @@ tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
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gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
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if (samples > VK_SAMPLE_COUNT_1_BIT)
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gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
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gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINE_MODE(RECTANGULAR);
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if (multiview) {
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gras_su_cntl |=
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@ -184,7 +184,8 @@ fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
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OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
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OUT_RING(ring,
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A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0) |
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COND(zsbuf->b.b.nr_samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
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A5XX_GRAS_SU_CNTL_LINE_MODE(zsbuf->b.b.nr_samples > 1 ?
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RECTANGULAR : BRESENHAM));
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OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
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OUT_RING(ring, 0x00000000);
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@ -667,7 +667,8 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
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OUT_RING(ring, rasterizer->gras_su_cntl |
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COND(pfb->samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
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A5XX_GRAS_SU_CNTL_LINE_MODE(pfb->samples > 1 ?
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RECTANGULAR : BRESENHAM));
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OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
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OUT_RING(ring, rasterizer->gras_su_point_minmax);
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@ -61,7 +61,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
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OUT_REG(ring,
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A6XX_GRAS_SU_CNTL(.linehalfwidth = cso->line_width / 2.0,
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.poly_offset = cso->offset_tri,
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.msaa_enable = cso->multisample,
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.line_mode = cso->multisample ? RECTANGULAR : BRESENHAM,
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.cull_front = cso->cull_face & PIPE_FACE_FRONT,
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.cull_back = cso->cull_face & PIPE_FACE_BACK,
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.front_cw = !cso->front_ccw, ));
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