diff --git a/src/intel/compiler/brw/brw_nir.c b/src/intel/compiler/brw/brw_nir.c
index a9a64d08b1a..0f8d596d0c9 100644
--- a/src/intel/compiler/brw/brw_nir.c
+++ b/src/intel/compiler/brw/brw_nir.c
@@ -354,12 +354,7 @@ try_load_push_input(nir_builder *b,
       offset_unit * nir_src_as_uint(nir_src_for_ssa(offset));
    assert((byte_offset % 4) == 0);
 
-   const enum mesa_shader_stage stage = b->shader->info.stage;
-   static const unsigned max_push_bytes[MESA_SHADER_MESH + 1] = {
-      [MESA_SHADER_TESS_EVAL] = 32 * 16 /* 32 vec4s */
-   };
-
-   if (byte_offset >= max_push_bytes[stage])
+   if (byte_offset >= cb_data->max_push_bytes)
       return NULL;
 
    return load_push_input(b, io, byte_offset);
@@ -978,6 +973,7 @@ brw_nir_lower_tes_inputs(nir_shader *nir,
    const struct brw_lower_urb_cb_data cb_data = {
       .devinfo = devinfo,
       .vec4_access = true,
+      .max_push_bytes = 32 * 16, /* 32 vec4s */
       .varying_to_slot = vue_map->varying_to_slot,
       .per_vertex_stride = vue_map->num_per_vertex_slots * 16,
       .dynamic_tes = vue_map->layout == INTEL_VUE_LAYOUT_SEPARATE,
diff --git a/src/intel/compiler/brw/brw_nir.h b/src/intel/compiler/brw/brw_nir.h
index 62194861114..556f481e62f 100644
--- a/src/intel/compiler/brw/brw_nir.h
+++ b/src/intel/compiler/brw/brw_nir.h
@@ -186,6 +186,9 @@ void brw_nir_lower_fs_barycentrics(nir_shader *shader);
 struct brw_lower_urb_cb_data {
    const struct intel_device_info *devinfo;
 
+   /** Maximum amount of pushed data in bytes */
+   unsigned max_push_bytes;
+
    /* If true, all access is guaranteed to be vec4 (128-bit) aligned.
     * offset and base are in units of 128-bit vec4 slots.
     *