fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 11:48:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

r600/sfn: Remove nir_register unit tests

Browse source 
These tests will be obsolete soon and are just extra users of an API that will
be removed. Drop them.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
This commit is contained in:
Alyssa Rosenzweig 2023-05-26 12:13:07 -04:00 • committed by Marge Bot
parent f334d00a8a
commit 886a7ae786
1 changed files with 0 additions and 102 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

102
src/gallium/drivers/r600/sfn/tests/sfn_valuefactory_test.cpp
View file

@ -69,108 +69,6 @@ TEST_F(ValuefactoryTest, test_create_ssa)
EXPECT_EQ(value->pin(), pin_none);
}
TEST_F(ValuefactoryTest, test_create_register_1)
{
nir_src src1 = NIR_SRC_INIT;
src1.reg.reg = nir_local_reg_create(b.impl);
src1.reg.reg->num_components = 1;
nir_src src2 = NIR_SRC_INIT;
src2.reg.reg = nir_local_reg_create(b.impl);
src2.reg.reg->num_components = 4;
ASSERT_FALSE(src1.is_ssa);
factory->allocate_registers(&b.impl->registers);
auto value = factory->src(src1, 0);
EXPECT_EQ(value->sel(), 1024);
EXPECT_EQ(value->chan(), 0);
for (int i = 0; i < 4; ++i) {
PVirtualValue value = factory->src(src2, i);
EXPECT_EQ(value->sel(), 1025);
EXPECT_EQ(value->chan(), i);
EXPECT_EQ(value->pin(), pin_none);
}
}
TEST_F(ValuefactoryTest, test_create_register_array_direct_access)
{
nir_dest dst = NIR_DEST_INIT;
dst.reg.reg = nir_local_reg_create(b.impl);
dst.reg.reg->num_components = 2;
dst.reg.reg->num_array_elems = 10;
factory->allocate_registers(&b.impl->registers);
auto c1 = nir_imm_float(&b, 2.0);
nir_alu_instr *mov = nir_alu_instr_create(b.shader, nir_op_mov);
mov->src[0].src = nir_src_for_ssa(c1);
mov->dest.write_mask = 3;
mov->dest.dest.is_ssa = false;
mov->dest.dest.reg.reg = dst.reg.reg;
mov->dest.dest.reg.base_offset = 5;
nir_builder_instr_insert(&b, &mov->instr);
auto regx = factory->dest(mov->dest.dest, 0, pin_none);
auto regy = factory->dest(mov->dest.dest, 1, pin_none);
EXPECT_EQ(regx->sel(), 1024 + 5);
EXPECT_EQ(regx->chan(), 0);
EXPECT_EQ(regx->pin(), pin_array);
EXPECT_EQ(regy->sel(), 1024 + 5);
EXPECT_EQ(regy->chan(), 1);
EXPECT_EQ(regy->pin(), pin_array);
}
TEST_F(ValuefactoryTest, test_create_register_array_indirect_access)
{
nir_dest dst = NIR_DEST_INIT;
dst.reg.reg = nir_local_reg_create(b.impl);
dst.reg.reg->num_components = 3;
dst.reg.reg->num_array_elems = 10;
factory->allocate_registers(&b.impl->registers);
auto c1 = nir_imm_vec2(&b, 2.0, 4.0);
auto c2 = nir_imm_int(&b, 3);
factory->dest(*c2, 0, pin_none);
nir_alu_instr *mov = nir_alu_instr_create(b.shader, nir_op_mov);
mov->src[0].src = nir_src_for_ssa(c1);
mov->dest.write_mask = 3;
mov->dest.dest.is_ssa = false;
mov->dest.dest.reg.reg = dst.reg.reg;
mov->dest.dest.reg.base_offset = 0;
mov->dest.dest.reg.indirect = (nir_src *)calloc(1, sizeof(nir_src));
nir_src addr = nir_src_for_ssa(c2);
nir_src_copy(mov->dest.dest.reg.indirect, &addr, &mov->instr);
nir_builder_instr_insert(&b, &mov->instr);
auto addr_reg = factory->src(addr, 0);
auto regx = factory->dest(mov->dest.dest, 0, pin_none);
auto regy = factory->dest(mov->dest.dest, 1, pin_none);
auto regx_addr = regx->get_addr();
ASSERT_TRUE(regx_addr);
EXPECT_EQ(regx->sel(), 1024);
EXPECT_EQ(regx->chan(), 0);
EXPECT_EQ(*regx_addr, *addr_reg);
EXPECT_EQ(regx->pin(), pin_array);
auto regy_addr = regy->get_addr();
ASSERT_TRUE(regy_addr);
EXPECT_EQ(regy->sel(), 1024);
EXPECT_EQ(regy->chan(), 1);
EXPECT_EQ(*regy_addr, *addr_reg);
EXPECT_EQ(regy->pin(), pin_array);
}
TEST_F(ValuefactoryTest, test_create_ssa_pinned_chan)
{
auto c1 = nir_imm_float(&b, 2.0);