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tu: Disable fragmentShadingRateWithShaderSampleMask due to issues

Browse source 
FSR with VK_EXT_post_depth_coverage enabled has wrong values of
gl_SampleMaskIn[0]. Prop driver has fragmentShadingRateWithShaderSampleMask
enabled, but it doesn't support VK_EXT_post_depth_coverage.

Sample mask is supplied by HW and there is no flag in sight to fix it.

The failing tests were:
 dEQP-VK.pipeline.fast_linked_library.multisample_with_fragment_shading_rate.sample_mask_with_depth_test.samples_2_post_depth_coverage
 dEQP-VK.pipeline.fast_linked_library.multisample_with_fragment_shading_rate.sample_mask_with_depth_test.samples_4_post_depth_coverage
 dEQP-VK.pipeline.monolithic.multisample_with_fragment_shading_rate.sample_mask_with_depth_test.samples_2_post_depth_coverage
 dEQP-VK.pipeline.monolithic.multisample_with_fragment_shading_rate.sample_mask_with_depth_test.samples_4_post_depth_coverage
 dEQP-VK.pipeline.pipeline_library.multisample_with_fragment_shading_rate.sample_mask_with_depth_test.samples_2_post_depth_coverage
 dEQP-VK.pipeline.pipeline_library.multisample_with_fragment_shading_rate.sample_mask_with_depth_test.samples_4_post_depth_coverage

Fixes: 2ab8eff511
("tu/a7xx: Implement VK_KHR_fragment_shading_rate")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32335>
This commit is contained in:
Danylo Piliaiev 2024-11-25 15:14:58 +01:00 • committed by Marge Bot
parent 239c0124df
commit 8858b16e4a
7 changed files with 34 additions and 8 deletions
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1
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -2869,6 +2869,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
break;
case nir_intrinsic_load_sample_mask_in:
if (!ctx->samp_mask_in) {
ctx->so->reads_smask = true;
ctx->samp_mask_in =
create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
}

1
src/freedreno/ir3/ir3_shader.h
View file

@ -742,6 +742,7 @@ struct ir3_shader_variant {
} inputs[32 + 2]; /* +POSITION +FACE */
bool reads_primid;
bool reads_shading_rate;
bool reads_smask;
/* sum of input components (scalar). For frag shaders, it only counts
* the varying inputs:

6
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -3722,11 +3722,15 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
if (pipeline->program.writes_shading_rate !=
cmd->state.pipeline_writes_shading_rate ||
pipeline->program.reads_shading_rate !=
cmd->state.pipeline_reads_shading_rate) {
cmd->state.pipeline_reads_shading_rate ||
pipeline->program.accesses_smask !=
cmd->state.pipeline_accesses_smask) {
cmd->state.pipeline_writes_shading_rate =
pipeline->program.writes_shading_rate;
cmd->state.pipeline_reads_shading_rate =
pipeline->program.reads_shading_rate;
cmd->state.pipeline_accesses_smask =
pipeline->program.accesses_smask;
cmd->state.dirty |= TU_CMD_DIRTY_SHADING_RATE;
}

1
src/freedreno/vulkan/tu_cmd_buffer.h
View file

@ -517,6 +517,7 @@ struct tu_cmd_state
VkImageAspectFlags pipeline_feedback_loops;
bool pipeline_writes_shading_rate;
bool pipeline_reads_shading_rate;
bool pipeline_accesses_smask;
bool pipeline_blend_lrz, pipeline_bandwidth;
uint32_t pipeline_draw_states;

3
src/freedreno/vulkan/tu_device.cc
View file

@ -1073,7 +1073,8 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->maxFragmentShadingRateRasterizationSamples = VK_SAMPLE_COUNT_4_BIT;
props->fragmentShadingRateWithShaderDepthStencilWrites = true;
props->fragmentShadingRateWithSampleMask = true;
props->fragmentShadingRateWithShaderSampleMask = true;
/* Has wrong gl_SampleMaskIn[0] values with VK_EXT_post_depth_coverage used. */
props->fragmentShadingRateWithShaderSampleMask = false;
props->fragmentShadingRateWithConservativeRasterization = false;
props->fragmentShadingRateWithFragmentShaderInterlock = false;
props->fragmentShadingRateWithCustomSampleLocations = true;

29
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -2305,6 +2305,7 @@ tu_emit_program_state(struct tu_cs *sub_cs,
dev->physical_device->info->a6xx.has_per_view_viewport;
prog->writes_shading_rate = last_shader->writes_shading_rate;
prog->reads_shading_rate = fs->reads_shading_rate;
prog->accesses_smask = fs->reads_smask || fs->writes_smask;
}
static const enum mesa_vk_dynamic_graphics_state tu_vertex_input_state[] = {
@ -3352,7 +3353,8 @@ tu6_fragment_shading_rate_size(struct tu_device *dev,
const vk_fragment_shading_rate_state *fsr,
bool enable_att_fsr,
bool enable_prim_fsr,
bool fs_reads_fsr)
bool fs_reads_fsr,
bool sample_shading)
{
return 6;
}
@ -3363,7 +3365,8 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs,
const vk_fragment_shading_rate_state *fsr,
bool enable_att_fsr,
bool enable_prim_fsr,
bool fs_reads_fsr)
bool fs_reads_fsr,
bool accesses_smask)
{
/* gl_ShadingRateEXT don't read 1x1 value with null config, so
* if it is read - we have to emit the config.
@ -3375,6 +3378,9 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs,
return;
}
uint32_t frag_width = fsr->fragment_size.width;
uint32_t frag_height = fsr->fragment_size.height;
bool enable_draw_fsr = true;
if (enable_att_fsr) {
if (fsr->combiner_ops[1] ==
@ -3396,6 +3402,15 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs,
}
}
/* Force 1x1 FSR because we don't support
* fragmentShadingRateWithShaderSampleMask.
*/
if (accesses_smask) {
enable_att_fsr = enable_prim_fsr = false;
frag_width = frag_height = 1;
enable_draw_fsr = true;
}
tu_cs_emit_regs(
cs,
A6XX_RB_FSR_CONFIG(.unk2 = true, .pipeline_fsr_enable = enable_draw_fsr,
@ -3408,8 +3423,8 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs,
tu_cs_emit_regs(
cs, A7XX_GRAS_FSR_CONFIG(
.pipeline_fsr_enable = enable_draw_fsr,
.frag_size_x = util_logbase2(fsr->fragment_size.width),
.frag_size_y = util_logbase2(fsr->fragment_size.height),
.frag_size_x = util_logbase2(frag_width),
.frag_size_y = util_logbase2(frag_height),
.combiner_op_1 = (a6xx_fsr_combiner) fsr->combiner_ops[0],
.combiner_op_2 = (a6xx_fsr_combiner) fsr->combiner_ops[1],
.attachment_fsr_enable = enable_att_fsr,
@ -3613,7 +3628,8 @@ tu_pipeline_builder_emit_state(struct tu_pipeline_builder *builder,
builder->graphics_state.fsr,
has_fsr_att,
pipeline->program.writes_shading_rate,
pipeline->program.reads_shading_rate);
pipeline->program.reads_shading_rate,
pipeline->program.accesses_smask);
}
#undef DRAW_STATE
#undef DRAW_STATE_COND
@ -3789,7 +3805,8 @@ tu_emit_draw_state(struct tu_cmd_buffer *cmd)
&cmd->vk.dynamic_graphics_state.fsr,
cmd->state.subpass->fsr_attachment != VK_ATTACHMENT_UNUSED,
cmd->state.program.writes_shading_rate,
cmd->state.program.reads_shading_rate);
cmd->state.program.reads_shading_rate,
cmd->state.program.accesses_smask);
}
DRAW_STATE_COND(rast, TU_DYNAMIC_STATE_RAST,
cmd->state.dirty & (TU_CMD_DIRTY_SUBPASS |

1
src/freedreno/vulkan/tu_pipeline.h
View file

@ -104,6 +104,7 @@ struct tu_program_state
bool per_view_viewport;
bool writes_shading_rate;
bool reads_shading_rate;
bool accesses_smask;
};
struct tu_pipeline_executable {