asahi: rework VBO lower for divisor=0

silly special case that we should handle.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29179>
This commit is contained in:
Alyssa Rosenzweig 2024-04-11 21:11:17 -04:00 committed by Marge Bot
parent 602d9b98d8
commit 883b5407c8
5 changed files with 13 additions and 4 deletions

View file

@ -47,7 +47,7 @@ struct agx_velem_key {
uint32_t divisor;
uint16_t stride;
uint8_t format;
uint8_t pad;
bool instanced;
};
struct agx_vs_prolog_key {

View file

@ -157,8 +157,12 @@ pass(struct nir_builder *b, nir_intrinsic_instr *intr, void *data)
* the divisor for per-instance data. Divisor=0 specifies per-vertex data.
*/
nir_def *el;
if (attrib.divisor) {
el = nir_udiv_imm(b, nir_load_instance_id(b), attrib.divisor);
if (attrib.instanced) {
if (attrib.divisor > 0)
el = nir_udiv_imm(b, nir_load_instance_id(b), attrib.divisor);
else
el = nir_imm_int(b, 0);
el = nir_iadd(b, el, nir_load_base_instance(b));
BITSET_SET(b->shader->info.system_values_read,

View file

@ -21,13 +21,16 @@ extern "C" {
* be small so it can be embedded into a shader key.
*/
struct agx_attribute {
/* If instanced, Zero means all get the same value (Vulkan semantics). */
uint32_t divisor;
uint32_t stride;
uint16_t src_offset;
uint8_t buf;
/* pipe_format, all vertex formats should be <= 255 */
uint8_t format;
unsigned buf : 7;
bool instanced : 1;
};
bool agx_nir_lower_vbo(nir_shader *shader, struct agx_attribute *attribs);

View file

@ -65,6 +65,7 @@ lower_vbo(nir_shader *s, const struct agx_velem_key *key)
.divisor = key[i].divisor,
.stride = key[i].stride,
.format = key[i].format,
.instanced = key[i].instanced,
};
}

View file

@ -1447,6 +1447,7 @@ agx_create_vertex_elements(struct pipe_context *ctx, unsigned count,
.stride = ve.src_stride,
.format = ve.src_format,
.divisor = ve.instance_divisor,
.instanced = ve.instance_divisor > 0,
};
}