diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c
index c4b772613fa..3d440ef8e08 100644
--- a/src/amd/common/ac_nir_lower_ngg.c
+++ b/src/amd/common/ac_nir_lower_ngg.c
@@ -1120,8 +1120,6 @@ analyze_shader_before_culling_walk(nir_def *ssa,
 static void
 analyze_shader_before_culling(nir_shader *shader, lower_ngg_nogs_state *s)
 {
-   /* LCSSA is needed to get correct results from divergence analysis. */
-   nir_convert_to_lcssa(shader, true, true);
    /* We need divergence info for culling shaders. */
    nir_divergence_analysis(shader);
 
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5e3bd306263..fb4206031cb 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -446,10 +446,9 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
 
    bool fix_derivs_in_divergent_cf =
       stage->stage == MESA_SHADER_FRAGMENT && !radv_use_llvm_for_stage(pdev, stage->stage);
-   if (fix_derivs_in_divergent_cf) {
-      NIR_PASS(_, stage->nir, nir_convert_to_lcssa, true, true);
+   if (fix_derivs_in_divergent_cf)
       nir_divergence_analysis(stage->nir);
-   }
+
    NIR_PASS(_, stage->nir, ac_nir_lower_tex,
             &(ac_nir_lower_tex_options){
                .gfx_level = gfx_level,
@@ -457,8 +456,6 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
                .fix_derivs_in_divergent_cf = fix_derivs_in_divergent_cf,
                .max_wqm_vgprs = 64, // TODO: improve spiller and RA support for linear VGPRs
             });
-   if (fix_derivs_in_divergent_cf)
-      NIR_PASS(_, stage->nir, nir_opt_remove_phis); /* cleanup LCSSA phis */
 
    if (stage->nir->info.uses_resource_info_query)
       NIR_PASS(_, stage->nir, ac_nir_lower_resinfo, gfx_level);
@@ -577,17 +574,12 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
    NIR_PASS(_, stage->nir, nir_lower_fp16_casts, nir_lower_fp16_split_fp64);
 
    if (stage->nir->info.bit_sizes_int & (8 | 16)) {
-      if (gfx_level >= GFX8) {
-         NIR_PASS(_, stage->nir, nir_convert_to_lcssa, true, true);
+      if (gfx_level >= GFX8)
          nir_divergence_analysis(stage->nir);
-      }
 
       if (nir_lower_bit_size(stage->nir, lower_bit_size_callback, device)) {
          NIR_PASS(_, stage->nir, nir_opt_constant_folding);
       }
-
-      if (gfx_level >= GFX8)
-         NIR_PASS(_, stage->nir, nir_opt_remove_phis); /* cleanup LCSSA phis */
    }
    if (gfx_level >= GFX9) {
       bool separate_g16 = gfx_level >= GFX10;
diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index bcb76ab810e..6ec9add0053 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -2969,7 +2969,6 @@ agx_optimize_nir(nir_shader *nir, bool soft_fault, unsigned *preamble_size)
             });
    NIR_PASS(_, nir, nir_lower_pack);
 
-   nir_convert_to_lcssa(nir, true, true);
    NIR_PASS_V(nir, nir_divergence_analysis);
    bool progress = false;
 
diff --git a/src/compiler/nir/nir_opt_non_uniform_access.c b/src/compiler/nir/nir_opt_non_uniform_access.c
index 46bdee8a3e0..2c2a1de000c 100644
--- a/src/compiler/nir/nir_opt_non_uniform_access.c
+++ b/src/compiler/nir/nir_opt_non_uniform_access.c
@@ -231,14 +231,11 @@ nir_opt_non_uniform_access_instr(nir_builder *b, nir_instr *instr, UNUSED void *
 bool
 nir_opt_non_uniform_access(nir_shader *shader)
 {
-   NIR_PASS(_, shader, nir_convert_to_lcssa, true, true);
    nir_divergence_analysis(shader);
 
    bool progress = nir_shader_instructions_pass(shader,
                                                 nir_opt_non_uniform_access_instr,
                                                 nir_metadata_all, NULL);
 
-   NIR_PASS(_, shader, nir_opt_remove_phis); /* cleanup LCSSA phis */
-
    return progress;
 }
diff --git a/src/compiler/nir/nir_opt_varyings.c b/src/compiler/nir/nir_opt_varyings.c
index 5732d9de8b9..c21b0e157bf 100644
--- a/src/compiler/nir/nir_opt_varyings.c
+++ b/src/compiler/nir/nir_opt_varyings.c
@@ -4328,8 +4328,6 @@ nir_opt_varyings(nir_shader *producer, nir_shader *consumer, bool spirv,
     * divergence information.
     */
    if (consumer->info.stage == MESA_SHADER_FRAGMENT) {
-      /* Required by the divergence analysis. */
-      NIR_PASS(_, producer, nir_convert_to_lcssa, true, true);
       nir_vertex_divergence_analysis(producer);
    }
 
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 67fbb80f45f..2e4832bdfec 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -480,7 +480,6 @@ char *si_finalize_nir(struct pipe_screen *screen, void *nirptr)
    if (progress)
       si_nir_opts(sscreen, nir, false);
 
-   NIR_PASS_V(nir, nir_convert_to_lcssa, true, true); /* required by divergence analysis */
    NIR_PASS_V(nir, nir_divergence_analysis); /* to find divergent loops */
 
    /* Must be after divergence analysis. */
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 0ef2a61f25a..2bb54673a4e 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -1596,9 +1596,6 @@ brw_vectorize_lower_mem_access(nir_shader *nir,
 
    OPT(nir_opt_load_store_vectorize, &options);
 
-   /* Required for nir_divergence_analysis() */
-   OPT(nir_convert_to_lcssa, true, true);
-
    /* When HW supports block loads, using the divergence analysis, try
     * to find uniform SSBO loads and turn them into block loads.
     *
@@ -1612,7 +1609,6 @@ brw_vectorize_lower_mem_access(nir_shader *nir,
    nir_divergence_analysis(nir);
    if (OPT(intel_nir_blockify_uniform_loads, compiler->devinfo))
       OPT(nir_opt_load_store_vectorize, &options);
-   OPT(nir_opt_remove_phis);
 
    nir_lower_mem_access_bit_sizes_options mem_access_options = {
       .modes = nir_var_mem_ssbo |
@@ -1783,7 +1779,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
    OPT(nir_opt_dead_cf);
 
    bool divergence_analysis_dirty = false;
-   NIR_PASS(_, nir, nir_convert_to_lcssa, true, true);
    NIR_PASS_V(nir, nir_divergence_analysis);
 
    static const nir_lower_subgroups_options subgroups_options = {
@@ -1833,16 +1828,12 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
    /* Do this only after the last opt_gcm. GCM will undo this lowering. */
    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
       if (divergence_analysis_dirty) {
-         NIR_PASS(_, nir, nir_convert_to_lcssa, true, true);
          NIR_PASS_V(nir, nir_divergence_analysis);
       }
 
       OPT(intel_nir_lower_non_uniform_barycentric_at_sample);
    }
 
-   /* Clean up LCSSA phis */
-   OPT(nir_opt_remove_phis);
-
    OPT(nir_lower_bool_to_int32);
    OPT(nir_copy_prop);
    OPT(nir_opt_dce);
diff --git a/src/intel/compiler/elk/elk_nir.c b/src/intel/compiler/elk/elk_nir.c
index c3fec24ece9..cdf0cce0d37 100644
--- a/src/intel/compiler/elk/elk_nir.c
+++ b/src/intel/compiler/elk/elk_nir.c
@@ -1464,7 +1464,6 @@ elk_postprocess_nir(nir_shader *nir, const struct elk_compiler *compiler,
    OPT(nir_opt_dead_cf);
 
    bool divergence_analysis_dirty = false;
-   NIR_PASS(_, nir, nir_convert_to_lcssa, true, true);
    NIR_PASS_V(nir, nir_divergence_analysis);
 
    /* TODO: Enable nir_opt_uniform_atomics on Gfx7.x too.
@@ -1489,16 +1488,12 @@ elk_postprocess_nir(nir_shader *nir, const struct elk_compiler *compiler,
    /* Do this only after the last opt_gcm. GCM will undo this lowering. */
    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
       if (divergence_analysis_dirty) {
-         NIR_PASS(_, nir, nir_convert_to_lcssa, true, true);
          NIR_PASS_V(nir, nir_divergence_analysis);
       }
 
       OPT(intel_nir_lower_non_uniform_barycentric_at_sample);
    }
 
-   /* Clean up LCSSA phis */
-   OPT(nir_opt_remove_phis);
-
    OPT(nir_lower_bool_to_int32);
    OPT(nir_copy_prop);
    OPT(nir_opt_dce);
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 3a827361ad0..4fb795a6abd 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1113,16 +1113,11 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
       NIR_PASS(progress, nir, nir_opt_dce);
    } while (progress);
 
-   /* Required for nir_divergence_analysis() which is needed for
-    * anv_nir_lower_ubo_loads.
-    */
-   NIR_PASS(_, nir, nir_convert_to_lcssa, true, true);
+   /* Needed for anv_nir_lower_ubo_loads. */
    nir_divergence_analysis(nir);
 
    NIR_PASS(_, nir, anv_nir_lower_ubo_loads);
 
-   NIR_PASS(_, nir, nir_opt_remove_phis);
-
    enum nir_lower_non_uniform_access_type lower_non_uniform_access_types =
       nir_lower_non_uniform_texture_access |
       nir_lower_non_uniform_image_access |
diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c
index 08b86749f75..1886a5151e1 100644
--- a/src/panfrost/compiler/bifrost_compile.c
+++ b/src/panfrost/compiler/bifrost_compile.c
@@ -4816,7 +4816,6 @@ bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
                         nir->info.images_used[0];
 
    if (any_indirects) {
-      nir_convert_to_lcssa(nir, true, true);
       NIR_PASS_V(nir, nir_divergence_analysis);
       NIR_PASS_V(nir, bi_lower_divergent_indirects,
                  pan_subgroup_size(pan_arch(gpu_id)));