From 87b938ce4109eb189b5cc702dfdc9d9d35d72a32 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 2 Jan 2026 15:55:38 +0100 Subject: [PATCH] ac/perfcounter: update configuration of many blocks on GFX10 Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_perfcounter.c | 3 +- src/amd/common/ac_perfcounter_gfx10.c | 58 +++++++++++++-------------- 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/src/amd/common/ac_perfcounter.c b/src/amd/common/ac_perfcounter.c index 35789053947..481176ae7e0 100644 --- a/src/amd/common/ac_perfcounter.c +++ b/src/amd/common/ac_perfcounter.c @@ -767,7 +767,8 @@ bool ac_init_perfcounters(const struct radeon_info *info, if (info->family == CHIP_NAVI21 || info->family == CHIP_NAVI31) { block->num_instances = 4; - } else if (info->family == CHIP_NAVI32 || + } else if (info->family == CHIP_NAVI14 || + info->family == CHIP_NAVI32 || info->family == CHIP_NAVI33) { block->num_instances = 2; } diff --git a/src/amd/common/ac_perfcounter_gfx10.c b/src/amd/common/ac_perfcounter_gfx10.c index d441da989f1..74639e1373c 100644 --- a/src/amd/common/ac_perfcounter_gfx10.c +++ b/src/amd/common/ac_perfcounter_gfx10.c @@ -785,35 +785,35 @@ static struct ac_pc_block_base gfx10_GCEA = { }; static struct ac_pc_block_gfxdescr groups_gfx10[] = { - {&gfx10_CB, 461}, - {&gfx10_CHA, 45}, - {&gfx10_CHCG, 35}, - {&gfx10_CHC, 35, 4}, - {&gfx10_CPC, 47}, - {&gfx10_CPF, 40}, - {&gfx10_CPG, 82}, - {&gfx10_DB, 370}, - {&gfx10_GCR, 94}, - {&gfx10_GDS, 123}, - {&gfx10_GE, 315}, - {&gfx10_GL1A, 36}, - {&gfx10_GL1C, 64, 4}, - {&gfx10_GL2A, 91}, - {&gfx10_GL2C, 235}, - {&gfx10_GRBM, 47}, - {&gfx10_GRBMSE, 19}, - {&gfx10_PA_PH, 960}, - {&gfx10_PA_SC, 552, 2}, - {&gfx10_PA_SU, 266}, - {&gfx10_RLC, 7}, - {&gfx10_RMI, 258}, - {&gfx10_SPI, 329}, - {&gfx10_SQ, 509}, - {&gfx10_SX, 225}, - {&gfx10_TA, 226}, - {&gfx10_TCP, 77}, - {&gfx10_TD, 61}, - {&gfx10_UTCL1, 15}, + {&gfx10_CB, 452}, + {&gfx10_CHA, 44}, + {&gfx10_CHCG, 34}, + {&gfx10_CHC, 34, 4}, + {&gfx10_CPC, 46}, + {&gfx10_CPF, 39}, + {&gfx10_CPG, 81}, + {&gfx10_DB, 369}, + {&gfx10_GCR, 93}, + {&gfx10_GDS, 120}, + {&gfx10_GE, 314}, + {&gfx10_GL1A, 35}, + {&gfx10_GL1C, 63, 4}, + {&gfx10_GL2A, 90}, + {&gfx10_GL2C, 234}, + {&gfx10_GRBM, 46}, + {&gfx10_GRBMSE, 18}, + {&gfx10_PA_PH, 959}, + {&gfx10_PA_SC, 551, 2}, + {&gfx10_PA_SU, 265}, + {&gfx10_RLC, 6}, + {&gfx10_RMI, 257}, + {&gfx10_SPI, 328}, + {&gfx10_SQ, 511}, + {&gfx10_SX, 224}, + {&gfx10_TA, 225}, + {&gfx10_TCP, 76}, + {&gfx10_TD, 60}, + {&gfx10_UTCL1, 14}, {&gfx10_GCEA, 88}, };