From 87b0962fef4e447a2ea9c76a611aa20b109a259d Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 28 Jul 2021 15:08:38 +0200 Subject: [PATCH] radv: do not use radeon_set_context_reg_seq() for only one register radeon_set_context_reg() is a shortcut for that. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 9 +++------ src/amd/vulkan/si_cmd_buffer.c | 10 +++++----- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 3e9f128a7e3..9b9efd43f18 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1728,8 +1728,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, radeon_emit(cmd_buffer->cs, cb->cb_color_fmask); radeon_emit(cmd_buffer->cs, 0); - radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1); - radeon_emit(cmd_buffer->cs, cb->cb_dcc_base); + radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base); radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4, cb->cb_color_base >> 32); @@ -1956,12 +1955,10 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cs, ds_clear_value.stencil); radeon_emit(cs, fui(ds_clear_value.depth)); } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) { - radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1); - radeon_emit(cs, fui(ds_clear_value.depth)); + radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(ds_clear_value.depth)); } else { assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT); - radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1); - radeon_emit(cs, ds_clear_value.stencil); + radeon_set_context_reg(cs, R_028028_DB_STENCIL_CLEAR, ds_clear_value.stencil); } /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index bd0021ed611..9d8825b57b7 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -542,11 +542,11 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) } unsigned tmp = (unsigned)(1.0 * 8.0); - radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1); - radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); - radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1); - radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | - S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875 / 2))); + radeon_set_context_reg(cs, R_028A00_PA_SU_POINT_SIZE, + S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); + radeon_set_context_reg(cs, R_028A04_PA_SU_POINT_MINMAX, + S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | + S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875 / 2))); if (!has_clear_state) { radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL, S_028004_ZPASS_INCREMENT_DISABLE(1));