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radv: mark all tess output for an indirect access.

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If a shader does a tcs store with an indirect access, we
were only marking the first spot as used. For indirect access
we always now mark all slots used by the variable.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464
Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 27a5e5366e)
Emil Velikov: move hunks {radv,ac}_nir_to_llvm.c]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/vulkan/radv_nir_to_llvm.c
This commit is contained in:
Dave Airlie 2018-03-14 10:21:46 +10:00 • committed by Emil Velikov
parent 14f55a8221
commit 876880b752
1 changed files with 13 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
src/amd/common/ac_nir_to_llvm.c
View file

@ -2846,13 +2846,14 @@ static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
static void
mark_tess_output(struct nir_to_llvm_context *ctx,
bool is_patch, uint32_t param)
bool is_patch, uint32_t param, int num_slots)
{
uint64_t slot_mask = (1ull << num_slots) - 1;
if (is_patch) {
ctx->tess_patch_outputs_written |= (1ull << param);
ctx->tess_patch_outputs_written |= (slot_mask << param);
} else
ctx->tess_outputs_written |= (1ull << param);
ctx->tess_outputs_written |= (slot_mask<< param);
}
static LLVMValueRef
@ -2948,6 +2949,7 @@ store_tcs_output(struct ac_shader_abi *abi,
const unsigned component = var->data.location_frac;
const bool is_patch = var->data.patch;
const bool is_compact = var->data.compact;
const unsigned count = glsl_count_attribute_slots(var->type, false);
LLVMValueRef dw_addr;
LLVMValueRef stride = NULL;
LLVMValueRef buf_addr = NULL;
@ -2976,7 +2978,10 @@ store_tcs_output(struct ac_shader_abi *abi,
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
}
mark_tess_output(ctx, is_patch, param);
if (param_index)
mark_tess_output(ctx, is_patch, param, count);
else
mark_tess_output(ctx, is_patch, param, 1);
dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
param_index);
@ -6223,9 +6228,9 @@ handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
if (i == VARYING_SLOT_CLIP_DIST0)
length = ctx->num_output_clips + ctx->num_output_culls;
int param = shader_io_get_unique_index(i);
mark_tess_output(ctx, false, param);
mark_tess_output(ctx, false, param, 1);
if (length > 4)
mark_tess_output(ctx, false, param + 1);
mark_tess_output(ctx, false, param + 1, 1);
LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
LLVMConstInt(ctx->ac.i32, param * 4, false),
"");
@ -6368,8 +6373,8 @@ write_tess_factors(struct nir_to_llvm_context *ctx)
tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
mark_tess_output(ctx, true, tess_inner_index);
mark_tess_output(ctx, true, tess_outer_index);
mark_tess_output(ctx, true, tess_inner_index, 1);
mark_tess_output(ctx, true, tess_outer_index, 1);
lds_base = get_tcs_out_current_patch_data_offset(ctx);
lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");