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radv: fix emitting SPI_SHADER_GS_OUT_CONFIG_PS with NULL FS on GFX12

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This register wasn't emitted at all if the fragment shader was NULL
and this was causing random GPU hangs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33030>
This commit is contained in:
Samuel Pitoiset 2025-01-15 01:58:12 -08:00 • committed by Marge Bot
parent 079f55d405
commit 874d34cf1b
1 changed files with 9 additions and 3 deletions
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12
src/amd/vulkan/radv_cmd_buffer.c
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@ -2576,9 +2576,6 @@ radv_emit_ps_inputs(struct radv_cmd_buffer *cmd_buffer)
assert(pdev->info.gfx_level >= GFX10_3 || num_per_primitive_params == 0);
if (pdev->info.gfx_level >= GFX12) {
radeon_set_sh_reg(cmd_buffer->cs, R_00B0C4_SPI_SHADER_GS_OUT_CONFIG_PS,
last_vgt_shader->info.regs.spi_vs_out_config | ps->info.regs.ps.spi_gs_out_config_ps);
radeon_opt_set_context_regn(cmd_buffer, R_028664_SPI_PS_INPUT_CNTL_0, ps_input_cntl,
cmd_buffer->tracked_regs.spi_ps_input_cntl, ps_offset);
} else {
@ -2843,6 +2840,15 @@ radv_emit_graphics_shaders(struct radv_cmd_buffer *cmd_buffer)
}
}
if (pdev->info.gfx_level >= GFX12) {
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
const struct radv_shader *last_vgt_shader = cmd_buffer->state.last_vgt_shader;
const uint32_t gs_out_config_ps =
last_vgt_shader->info.regs.spi_vs_out_config | (ps ? ps->info.regs.ps.spi_gs_out_config_ps : 0);
radeon_set_sh_reg(cmd_buffer->cs, R_00B0C4_SPI_SHADER_GS_OUT_CONFIG_PS, gs_out_config_ps);
}
const struct radv_vgt_shader_key vgt_shader_cfg_key =
radv_get_vgt_shader_key(device, cmd_buffer->state.shaders, cmd_buffer->state.gs_copy_shader);