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intel/brw: Stop using long BRW_REGISTER_TYPE enum names

Browse source 
s/BRW_REGISTER_TYPE/BRW_TYPE/g

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
This commit is contained in:
Kenneth Graunke 2024-04-20 17:08:02 -07:00 • committed by Marge Bot
parent 9d8f2c4421
commit 873fcdff38
42 changed files with 1996 additions and 2014 deletions
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52
src/intel/compiler/brw_disasm.c
View file

@ -843,7 +843,7 @@ dest(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
/* These are fixed for split sends */
type = BRW_REGISTER_TYPE_UD;
type = BRW_TYPE_UD;
elem_size = 4;
if (devinfo->ver >= 12) {
err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
@ -1234,11 +1234,11 @@ src0_3src(FILE *file, const struct intel_device_info *devinfo,
uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst);
enum brw_reg_type type = brw_inst_3src_a1_src0_type(devinfo, inst);
if (type == BRW_REGISTER_TYPE_W) {
if (type == BRW_TYPE_W) {
format(file, "%dW", imm_val);
} else if (type == BRW_REGISTER_TYPE_UW) {
} else if (type == BRW_TYPE_UW) {
format(file, "0x%04xUW", imm_val);
} else if (type == BRW_REGISTER_TYPE_HF) {
} else if (type == BRW_TYPE_HF) {
format(file, "0x%04xHF", imm_val);
}
return 0;
@ -1392,11 +1392,11 @@ src2_3src(FILE *file, const struct intel_device_info *devinfo,
uint16_t imm_val = brw_inst_3src_a1_src2_imm(devinfo, inst);
enum brw_reg_type type = brw_inst_3src_a1_src2_type(devinfo, inst);
if (type == BRW_REGISTER_TYPE_W) {
if (type == BRW_TYPE_W) {
format(file, "%dW", imm_val);
} else if (type == BRW_REGISTER_TYPE_UW) {
} else if (type == BRW_TYPE_UW) {
format(file, "0x%04xUW", imm_val);
} else if (type == BRW_REGISTER_TYPE_HF) {
} else if (type == BRW_TYPE_HF) {
format(file, "0x%04xHF", imm_val);
}
return 0;
@ -1531,28 +1531,28 @@ imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type,
const struct intel_device_info *devinfo = isa->devinfo;
switch (type) {
case BRW_REGISTER_TYPE_UQ:
case BRW_TYPE_UQ:
format(file, "0x%016"PRIx64"UQ", brw_inst_imm_uq(devinfo, inst));
break;
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_Q:
format(file, "0x%016"PRIx64"Q", brw_inst_imm_uq(devinfo, inst));
break;
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_UD:
format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));
break;
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
format(file, "%dD", brw_inst_imm_d(devinfo, inst));
break;
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_UW:
format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(devinfo, inst));
break;
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_W:
format(file, "%dW", (int16_t) brw_inst_imm_d(devinfo, inst));
break;
case BRW_REGISTER_TYPE_UV:
case BRW_TYPE_UV:
format(file, "0x%08xUV", brw_inst_imm_ud(devinfo, inst));
break;
case BRW_REGISTER_TYPE_VF:
case BRW_TYPE_VF:
format(file, "0x%"PRIx64"VF", brw_inst_bits(inst, 127, 96));
pad(file, 48);
format(file, "/* [%-gF, %-gF, %-gF, %-gF]VF */",
@ -1561,10 +1561,10 @@ imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type,
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24));
break;
case BRW_REGISTER_TYPE_V:
case BRW_TYPE_V:
format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst));
break;
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
/* The DIM instruction's src0 uses an F type but contains a
* 64-bit immediate
*/
@ -1572,20 +1572,20 @@ imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type,
pad(file, 48);
format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst));
break;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
format(file, "0x%016"PRIx64"DF", brw_inst_imm_uq(devinfo, inst));
pad(file, 48);
format(file, "/* %-gDF */", brw_inst_imm_df(devinfo, inst));
break;
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
format(file, "0x%04xHF",
(uint16_t) brw_inst_imm_ud(devinfo, inst));
pad(file, 48);
format(file, "/* %-gHF */",
_mesa_half_to_float((uint16_t) brw_inst_imm_ud(devinfo, inst)));
break;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case BRW_TYPE_UB:
case BRW_TYPE_B:
default:
format(file, "*** invalid immediate type %d ", type);
}
@ -1652,21 +1652,21 @@ src0(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
if (devinfo->ver >= 12) {
return src_sends_da(file,
devinfo,
BRW_REGISTER_TYPE_UD,
BRW_TYPE_UD,
brw_inst_send_src0_reg_file(devinfo, inst),
brw_inst_src0_da_reg_nr(devinfo, inst),
0);
} else if (brw_inst_send_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
return src_sends_da(file,
devinfo,
BRW_REGISTER_TYPE_UD,
BRW_TYPE_UD,
BRW_GENERAL_REGISTER_FILE,
brw_inst_src0_da_reg_nr(devinfo, inst),
brw_inst_src0_da16_subreg_nr(devinfo, inst));
} else {
return src_sends_ia(file,
devinfo,
BRW_REGISTER_TYPE_UD,
BRW_TYPE_UD,
brw_inst_send_src0_ia16_addr_imm(devinfo, inst),
brw_inst_src0_ia_subreg_nr(devinfo, inst));
}
@ -1730,7 +1730,7 @@ src1(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
return src_sends_da(file,
devinfo,
BRW_REGISTER_TYPE_UD,
BRW_TYPE_UD,
brw_inst_send_src1_reg_file(devinfo, inst),
brw_inst_send_src1_reg_nr(devinfo, inst),
0 /* subreg_nr */);
@ -1857,7 +1857,7 @@ swsb(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC ||
opcode == BRW_OPCODE_MATH || opcode == BRW_OPCODE_DPAS ||
(devinfo->has_64bit_float_via_math_pipe &&
inst_has_type(isa, inst, BRW_REGISTER_TYPE_DF));
inst_has_type(isa, inst, BRW_TYPE_DF));
const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, is_unordered, x);
if (swsb.regdist)
format(file, " %s@%d",

4
src/intel/compiler/brw_eu.c
View file

@ -96,10 +96,10 @@ brw_swap_cmod(enum brw_conditional_mod cmod)
static unsigned
imm_shift(enum brw_reg_type type, unsigned i)
{
assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
assert(type != BRW_TYPE_UV && type != BRW_TYPE_V &&
"Not implemented.");
if (type == BRW_REGISTER_TYPE_VF)
if (type == BRW_TYPE_VF)
return 8 * (i & 3);
else
return 0;

84
src/intel/compiler/brw_eu_compact.c
View file

@ -1463,9 +1463,9 @@ compact_immediate(const struct intel_device_info *devinfo,
* field
*/
switch (type) {
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_W:
case BRW_TYPE_UW:
case BRW_TYPE_HF:
if ((imm >> 16) != (imm & 0xffff))
return -1;
break;
@ -1474,44 +1474,44 @@ compact_immediate(const struct intel_device_info *devinfo,
}
switch (type) {
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
/* We get the high 12-bits as-is; rest must be zero */
if ((imm & 0xfffff) == 0)
return (imm >> 20) & 0xfff;
break;
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
/* We get the high 12-bits as-is; rest must be zero */
if ((imm & 0xf) == 0)
return (imm >> 4) & 0xfff;
break;
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_VF:
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_V:
case BRW_TYPE_UD:
case BRW_TYPE_VF:
case BRW_TYPE_UV:
case BRW_TYPE_V:
/* We get the low 12-bits as-is; rest must be zero */
if ((imm & 0xfffff000) == 0)
return imm & 0xfff;
break;
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_UW:
/* We get the low 12-bits as-is; rest must be zero */
if ((imm & 0xf000) == 0)
return imm & 0xfff;
break;
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
/* We get the low 11-bits as-is; 12th is replicated */
if (((int)imm >> 11) == 0 || ((int)imm >> 11) == -1)
return imm & 0xfff;
break;
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_W:
/* We get the low 11-bits as-is; 12th is replicated */
if (((short)imm >> 11) == 0 || ((short)imm >> 11) == -1)
return imm & 0xfff;
break;
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_UB:
case BRW_TYPE_DF:
case BRW_TYPE_Q:
case BRW_TYPE_UQ:
case BRW_TYPE_B:
case BRW_TYPE_UB:
default:
return -1;
}
@ -1531,30 +1531,30 @@ uncompact_immediate(const struct intel_device_info *devinfo,
{
if (devinfo->ver >= 12) {
switch (type) {
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
return compact_imm << 20;
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
return (compact_imm << 20) | (compact_imm << 4);
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_VF:
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_V:
case BRW_TYPE_UD:
case BRW_TYPE_VF:
case BRW_TYPE_UV:
case BRW_TYPE_V:
return compact_imm;
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_UW:
/* Replicate */
return compact_imm << 16 | compact_imm;
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
/* Extend the 12th bit into the high 20 bits */
return (int)(compact_imm << 20) >> 20;
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_W:
/* Extend the 12th bit into the high 4 bits and replicate */
return ((int)(compact_imm << 20) >> 4) |
((unsigned short)((short)(compact_imm << 4) >> 4));
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_UB:
case BRW_TYPE_DF:
case BRW_TYPE_Q:
case BRW_TYPE_UQ:
case BRW_TYPE_B:
case BRW_TYPE_UB:
unreachable("not reached");
default:
unreachable("invalid type");
@ -1640,9 +1640,9 @@ precompact(const struct brw_isa_info *isa, brw_inst inst)
* overlap with the immediate and setting them would overwrite the
* immediate we set.
*/
if (!(brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF ||
brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_UQ ||
brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_Q)) {
if (!(brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_DF ||
brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_UQ ||
brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_Q)) {
brw_inst_set_src1_reg_hw_type(devinfo, &inst, 0);
}
@ -1662,11 +1662,11 @@ precompact(const struct brw_isa_info *isa, brw_inst inst)
*/
if (devinfo->ver < 12 &&
brw_inst_imm_ud(devinfo, &inst) == 0x0 &&
brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_F &&
brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_F &&
brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_F &&
brw_inst_dst_type(devinfo, &inst) == BRW_TYPE_F &&
brw_inst_dst_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
enum brw_reg_file file = brw_inst_src0_reg_file(devinfo, &inst);
brw_inst_set_src0_file_type(devinfo, &inst, file, BRW_REGISTER_TYPE_VF);
brw_inst_set_src0_file_type(devinfo, &inst, file, BRW_TYPE_VF);
}
/* There are no mappings for dst:d | i:d, so if the immediate is suitable
@ -1675,16 +1675,16 @@ precompact(const struct brw_isa_info *isa, brw_inst inst)
* FINISHME: Use dst:f | imm:f on Gfx12
*/
if (devinfo->ver < 12 &&
compact_immediate(devinfo, BRW_REGISTER_TYPE_D,
compact_immediate(devinfo, BRW_TYPE_D,
brw_inst_imm_ud(devinfo, &inst)) != -1 &&
brw_inst_cond_modifier(devinfo, &inst) == BRW_CONDITIONAL_NONE &&
brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_D &&
brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_D) {
brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_D &&
brw_inst_dst_type(devinfo, &inst) == BRW_TYPE_D) {
enum brw_reg_file src_file = brw_inst_src0_reg_file(devinfo, &inst);
enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, &inst);
brw_inst_set_src0_file_type(devinfo, &inst, src_file, BRW_REGISTER_TYPE_UD);
brw_inst_set_dst_file_type(devinfo, &inst, dst_file, BRW_REGISTER_TYPE_UD);
brw_inst_set_src0_file_type(devinfo, &inst, src_file, BRW_TYPE_UD);
brw_inst_set_dst_file_type(devinfo, &inst, dst_file, BRW_TYPE_UD);
}
return inst;

168
src/intel/compiler/brw_eu_emit.c
View file

@ -179,10 +179,10 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
brw_inst_set_src0_address_mode(devinfo, inst, reg.address_mode);
if (reg.file == BRW_IMMEDIATE_VALUE) {
if (reg.type == BRW_REGISTER_TYPE_DF)
if (reg.type == BRW_TYPE_DF)
brw_inst_set_imm_df(devinfo, inst, reg.df);
else if (reg.type == BRW_REGISTER_TYPE_UQ ||
reg.type == BRW_REGISTER_TYPE_Q)
else if (reg.type == BRW_TYPE_UQ ||
reg.type == BRW_TYPE_Q)
brw_inst_set_imm_uq(devinfo, inst, reg.u64);
else
brw_inst_set_imm_ud(devinfo, inst, reg.ud);
@ -351,7 +351,7 @@ brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst,
brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC);
if (devinfo->ver < 12)
brw_inst_set_src1_file_type(devinfo, inst,
BRW_IMMEDIATE_VALUE, BRW_REGISTER_TYPE_UD);
BRW_IMMEDIATE_VALUE, BRW_TYPE_UD);
brw_inst_set_send_desc(devinfo, inst, desc);
if (devinfo->ver >= 9)
brw_inst_set_send_ex_desc(devinfo, inst, ex_desc);
@ -676,11 +676,11 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
} else {
assert(dest.file == BRW_GENERAL_REGISTER_FILE);
assert(dest.type == BRW_REGISTER_TYPE_F ||
dest.type == BRW_REGISTER_TYPE_DF ||
dest.type == BRW_REGISTER_TYPE_D ||
dest.type == BRW_REGISTER_TYPE_UD ||
dest.type == BRW_REGISTER_TYPE_HF);
assert(dest.type == BRW_TYPE_F ||
dest.type == BRW_TYPE_DF ||
dest.type == BRW_TYPE_D ||
dest.type == BRW_TYPE_UD ||
dest.type == BRW_TYPE_HF);
brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
brw_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 4);
brw_inst_set_3src_a16_dst_writemask(devinfo, inst, dest.writemask);
@ -731,10 +731,10 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
* 0b = :f. Single precision Float (32-bit).
* 1b = :hf. Half precision Float (16-bit)."
*/
if (src1.type == BRW_REGISTER_TYPE_HF)
if (src1.type == BRW_TYPE_HF)
brw_inst_set_3src_a16_src1_type(devinfo, inst, 1);
if (src2.type == BRW_REGISTER_TYPE_HF)
if (src2.type == BRW_TYPE_HF)
brw_inst_set_3src_a16_src2_type(devinfo, inst, 1);
}
@ -841,16 +841,16 @@ brw_inst *brw_##OP(struct brw_codegen *p, \
struct brw_reg src1, \
struct brw_reg src2) \
{ \
assert(dest.type == BRW_REGISTER_TYPE_F || \
dest.type == BRW_REGISTER_TYPE_DF); \
if (dest.type == BRW_REGISTER_TYPE_F) { \
assert(src0.type == BRW_REGISTER_TYPE_F); \
assert(src1.type == BRW_REGISTER_TYPE_F); \
assert(src2.type == BRW_REGISTER_TYPE_F); \
} else if (dest.type == BRW_REGISTER_TYPE_DF) { \
assert(src0.type == BRW_REGISTER_TYPE_DF); \
assert(src1.type == BRW_REGISTER_TYPE_DF); \
assert(src2.type == BRW_REGISTER_TYPE_DF); \
assert(dest.type == BRW_TYPE_F || \
dest.type == BRW_TYPE_DF); \
if (dest.type == BRW_TYPE_F) { \
assert(src0.type == BRW_TYPE_F); \
assert(src1.type == BRW_TYPE_F); \
assert(src2.type == BRW_TYPE_F); \
} else if (dest.type == BRW_TYPE_DF) { \
assert(src0.type == BRW_TYPE_DF); \
assert(src1.type == BRW_TYPE_DF); \
assert(src2.type == BRW_TYPE_DF); \
} \
\
if (p->current->access_mode == BRW_ALIGN_16) { \
@ -907,18 +907,18 @@ brw_ADD(struct brw_codegen *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)
{
/* 6.2.2: add */
if (src0.type == BRW_REGISTER_TYPE_F ||
if (src0.type == BRW_TYPE_F ||
(src0.file == BRW_IMMEDIATE_VALUE &&
src0.type == BRW_REGISTER_TYPE_VF)) {
assert(src1.type != BRW_REGISTER_TYPE_UD);
assert(src1.type != BRW_REGISTER_TYPE_D);
src0.type == BRW_TYPE_VF)) {
assert(src1.type != BRW_TYPE_UD);
assert(src1.type != BRW_TYPE_D);
}
if (src1.type == BRW_REGISTER_TYPE_F ||
if (src1.type == BRW_TYPE_F ||
(src1.file == BRW_IMMEDIATE_VALUE &&
src1.type == BRW_REGISTER_TYPE_VF)) {
assert(src0.type != BRW_REGISTER_TYPE_UD);
assert(src0.type != BRW_REGISTER_TYPE_D);
src1.type == BRW_TYPE_VF)) {
assert(src0.type != BRW_TYPE_UD);
assert(src0.type != BRW_TYPE_D);
}
return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
@ -931,12 +931,12 @@ brw_AVG(struct brw_codegen *p, struct brw_reg dest,
assert(dest.type == src0.type);
assert(src0.type == src1.type);
switch (src0.type) {
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_B:
case BRW_TYPE_UB:
case BRW_TYPE_W:
case BRW_TYPE_UW:
case BRW_TYPE_D:
case BRW_TYPE_UD:
break;
default:
unreachable("Bad type for brw_AVG");
@ -950,25 +950,25 @@ brw_MUL(struct brw_codegen *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)
{
/* 6.32.38: mul */
if (src0.type == BRW_REGISTER_TYPE_D ||
src0.type == BRW_REGISTER_TYPE_UD ||
src1.type == BRW_REGISTER_TYPE_D ||
src1.type == BRW_REGISTER_TYPE_UD) {
assert(dest.type != BRW_REGISTER_TYPE_F);
if (src0.type == BRW_TYPE_D ||
src0.type == BRW_TYPE_UD ||
src1.type == BRW_TYPE_D ||
src1.type == BRW_TYPE_UD) {
assert(dest.type != BRW_TYPE_F);
}
if (src0.type == BRW_REGISTER_TYPE_F ||
if (src0.type == BRW_TYPE_F ||
(src0.file == BRW_IMMEDIATE_VALUE &&
src0.type == BRW_REGISTER_TYPE_VF)) {
assert(src1.type != BRW_REGISTER_TYPE_UD);
assert(src1.type != BRW_REGISTER_TYPE_D);
src0.type == BRW_TYPE_VF)) {
assert(src1.type != BRW_TYPE_UD);
assert(src1.type != BRW_TYPE_D);
}
if (src1.type == BRW_REGISTER_TYPE_F ||
if (src1.type == BRW_TYPE_F ||
(src1.file == BRW_IMMEDIATE_VALUE &&
src1.type == BRW_REGISTER_TYPE_VF)) {
assert(src0.type != BRW_REGISTER_TYPE_UD);
assert(src0.type != BRW_REGISTER_TYPE_D);
src1.type == BRW_TYPE_VF)) {
assert(src0.type != BRW_TYPE_UD);
assert(src0.type != BRW_TYPE_D);
}
assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
@ -1106,7 +1106,7 @@ brw_IF(struct brw_codegen *p, unsigned execute_size)
/* Override the defaults for this instruction:
*/
brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_TYPE_D)));
if (devinfo->ver < 12)
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(devinfo, insn, 0);
@ -1184,7 +1184,7 @@ brw_ELSE(struct brw_codegen *p)
insn = next_insn(p, BRW_OPCODE_ELSE);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_TYPE_D));
if (devinfo->ver < 12)
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(devinfo, insn, 0);
@ -1252,7 +1252,7 @@ brw_BREAK(struct brw_codegen *p)
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_BREAK);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_TYPE_D));
brw_set_src0(p, insn, brw_imm_d(0x0));
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p));
@ -1282,7 +1282,7 @@ brw_HALT(struct brw_codegen *p)
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_HALT);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_TYPE_D));
if (devinfo->ver < 12) {
brw_set_src0(p, insn, brw_imm_d(0x0));
}
@ -1321,7 +1321,7 @@ brw_WHILE(struct brw_codegen *p)
insn = next_insn(p, BRW_OPCODE_WHILE);
do_insn = get_inner_do_insn(p);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_TYPE_D));
if (devinfo->ver < 12)
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(devinfo, insn, br * (do_insn - insn));
@ -1385,8 +1385,8 @@ void gfx6_math(struct brw_codegen *p,
if (function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT ||
function == BRW_MATH_FUNCTION_INT_DIV_REMAINDER ||
function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
assert(src0.type != BRW_REGISTER_TYPE_F);
assert(src1.type != BRW_REGISTER_TYPE_F);
assert(src0.type != BRW_TYPE_F);
assert(src1.type != BRW_TYPE_F);
assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
src1.file == BRW_IMMEDIATE_VALUE);
/* From BSpec 6647/47428 "[Instruction] Extended Math Function":
@ -1397,10 +1397,10 @@ void gfx6_math(struct brw_codegen *p,
assert(!src1.negate);
assert(!src1.abs);
} else {
assert(src0.type == BRW_REGISTER_TYPE_F ||
(src0.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9));
assert(src1.type == BRW_REGISTER_TYPE_F ||
(src1.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9));
assert(src0.type == BRW_TYPE_F ||
(src0.type == BRW_TYPE_HF && devinfo->ver >= 9));
assert(src1.type == BRW_TYPE_F ||
(src1.type == BRW_TYPE_HF && devinfo->ver >= 9));
}
brw_inst_set_math_function(devinfo, insn, function);
@ -1422,17 +1422,17 @@ brw_send_indirect_message(struct brw_codegen *p,
const struct intel_device_info *devinfo = p->devinfo;
struct brw_inst *send;
dst = retype(dst, BRW_REGISTER_TYPE_UW);
dst = retype(dst, BRW_TYPE_UW);
assert(desc.type == BRW_REGISTER_TYPE_UD);
assert(desc.type == BRW_TYPE_UD);
if (desc.file == BRW_IMMEDIATE_VALUE) {
send = next_insn(p, BRW_OPCODE_SEND);
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, send, retype(payload, BRW_TYPE_UD));
brw_set_desc(p, send, desc.ud | desc_imm);
} else {
const struct tgl_swsb swsb = brw_get_default_swsb(p);
struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
struct brw_reg addr = retype(brw_address_reg(0), BRW_TYPE_UD);
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
@ -1452,7 +1452,7 @@ brw_send_indirect_message(struct brw_codegen *p,
brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
send = next_insn(p, BRW_OPCODE_SEND);
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, send, retype(payload, BRW_TYPE_UD));
if (devinfo->ver >= 12)
brw_inst_set_send_sel_reg32_desc(devinfo, send, true);
@ -1482,15 +1482,15 @@ brw_send_indirect_split_message(struct brw_codegen *p,
const struct intel_device_info *devinfo = p->devinfo;
struct brw_inst *send;
dst = retype(dst, BRW_REGISTER_TYPE_UW);
dst = retype(dst, BRW_TYPE_UW);
assert(desc.type == BRW_REGISTER_TYPE_UD);
assert(desc.type == BRW_TYPE_UD);
if (desc.file == BRW_IMMEDIATE_VALUE) {
desc.ud |= desc_imm;
} else {
const struct tgl_swsb swsb = brw_get_default_swsb(p);
struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
struct brw_reg addr = retype(brw_address_reg(0), BRW_TYPE_UD);
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
@ -1525,7 +1525,7 @@ brw_send_indirect_split_message(struct brw_codegen *p,
ex_desc.ud |= ex_desc_imm;
} else {
const struct tgl_swsb swsb = brw_get_default_swsb(p);
struct brw_reg addr = retype(brw_address_reg(2), BRW_REGISTER_TYPE_UD);
struct brw_reg addr = retype(brw_address_reg(2), BRW_TYPE_UD);
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
@ -1553,7 +1553,7 @@ brw_send_indirect_split_message(struct brw_codegen *p,
*/
assert(devinfo->verx10 >= 125);
brw_AND(p, addr,
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 5), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 10)));
brw_OR(p, addr, addr, brw_imm_ud(imm_part));
} else if (ex_desc.file == BRW_IMMEDIATE_VALUE) {
@ -1574,8 +1574,8 @@ brw_send_indirect_split_message(struct brw_codegen *p,
send = next_insn(p, devinfo->ver >= 12 ? BRW_OPCODE_SEND : BRW_OPCODE_SENDS);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, retype(payload0, BRW_REGISTER_TYPE_UD));
brw_set_src1(p, send, retype(payload1, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, send, retype(payload0, BRW_TYPE_UD));
brw_set_src1(p, send, retype(payload1, BRW_TYPE_UD));
if (desc.file == BRW_IMMEDIATE_VALUE) {
brw_inst_set_send_sel_reg32_desc(devinfo, send, 0);
@ -1861,8 +1861,8 @@ brw_memory_fence(struct brw_codegen *p,
{
const struct intel_device_info *devinfo = p->devinfo;
dst = retype(vec1(dst), BRW_REGISTER_TYPE_UW);
src = retype(vec1(src), BRW_REGISTER_TYPE_UD);
dst = retype(vec1(dst), BRW_TYPE_UW);
src = retype(vec1(src), BRW_TYPE_UD);
/* Set dst as destination for dependency tracking, the MEMORY_FENCE
* message doesn't write anything back.
@ -1907,7 +1907,7 @@ brw_broadcast(struct brw_codegen *p,
*/
assert(src.type == dst.type);
src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8,
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
if ((src.vstride == 0 && src.hstride == 0) ||
idx.file == BRW_IMMEDIATE_VALUE) {
@ -1919,11 +1919,11 @@ brw_broadcast(struct brw_codegen *p,
src = stride(suboffset(src, i), 0, 1, 0);
if (type_sz(src.type) > 4 && !devinfo->has_64bit_int) {
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
subscript(src, BRW_REGISTER_TYPE_D, 0));
brw_MOV(p, subscript(dst, BRW_TYPE_D, 0),
subscript(src, BRW_TYPE_D, 0));
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
subscript(src, BRW_REGISTER_TYPE_D, 1));
brw_MOV(p, subscript(dst, BRW_TYPE_D, 1),
subscript(src, BRW_TYPE_D, 1));
} else {
brw_MOV(p, dst, src);
}
@ -1943,7 +1943,7 @@ brw_broadcast(struct brw_codegen *p,
assert(src.subnr == 0);
const struct brw_reg addr =
retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
retype(brw_address_reg(0), BRW_TYPE_UD);
unsigned offset = src.nr * REG_SIZE + src.subnr;
/* Limit in bytes of the signed indirect addressing immediate. */
const unsigned limit = 512;
@ -1990,13 +1990,13 @@ brw_broadcast(struct brw_codegen *p,
* the indirect here to handle adding 4 bytes to the offset and
* avoid the extra ADD to the register file.
*/
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
brw_MOV(p, subscript(dst, BRW_TYPE_D, 0),
retype(brw_vec1_indirect(addr.subnr, offset),
BRW_REGISTER_TYPE_D));
BRW_TYPE_D));
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
brw_MOV(p, subscript(dst, BRW_TYPE_D, 1),
retype(brw_vec1_indirect(addr.subnr, offset + 4),
BRW_REGISTER_TYPE_D));
BRW_TYPE_D));
} else {
brw_MOV(p, dst,
retype(brw_vec1_indirect(addr.subnr, offset), src.type));
@ -2019,7 +2019,7 @@ brw_barrier(struct brw_codegen *p, struct brw_reg src)
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
inst = next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
brw_set_dest(p, inst, retype(brw_null_reg(), BRW_TYPE_UW));
brw_set_src0(p, inst, src);
brw_set_src1(p, inst, brw_null_reg());
brw_set_desc(p, inst, brw_message_desc(devinfo,

234
src/intel/compiler/brw_eu_validate.c
View file

@ -134,7 +134,7 @@ inst_dst_type(const struct brw_isa_info *isa, const brw_inst *inst)
const struct intel_device_info *devinfo = isa->devinfo;
return (devinfo->ver < 12 || !inst_is_send(isa, inst)) ?
brw_inst_dst_type(devinfo, inst) : BRW_REGISTER_TYPE_D;
brw_inst_dst_type(devinfo, inst) : BRW_TYPE_D;
}
static bool
@ -147,9 +147,9 @@ inst_is_raw_move(const struct brw_isa_info *isa, const brw_inst *inst)
if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
/* FIXME: not strictly true */
if (brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_VF ||
brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UV ||
brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_V) {
if (brw_inst_src0_type(devinfo, inst) == BRW_TYPE_VF ||
brw_inst_src0_type(devinfo, inst) == BRW_TYPE_UV ||
brw_inst_src0_type(devinfo, inst) == BRW_TYPE_V) {
return false;
}
} else if (brw_inst_src0_negate(devinfo, inst) ||
@ -431,37 +431,37 @@ is_unsupported_inst(const struct brw_isa_info *isa,
static inline bool
types_are_mixed_float(enum brw_reg_type t0, enum brw_reg_type t1)
{
return (t0 == BRW_REGISTER_TYPE_F && t1 == BRW_REGISTER_TYPE_HF) ||
(t1 == BRW_REGISTER_TYPE_F && t0 == BRW_REGISTER_TYPE_HF);
return (t0 == BRW_TYPE_F && t1 == BRW_TYPE_HF) ||
(t1 == BRW_TYPE_F && t0 == BRW_TYPE_HF);
}
static enum brw_reg_type
execution_type_for_type(enum brw_reg_type type)
{
switch (type) {
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_DF:
case BRW_TYPE_F:
case BRW_TYPE_HF:
return type;
case BRW_REGISTER_TYPE_VF:
return BRW_REGISTER_TYPE_F;
case BRW_TYPE_VF:
return BRW_TYPE_F;
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_UQ:
return BRW_REGISTER_TYPE_Q;
case BRW_TYPE_Q:
case BRW_TYPE_UQ:
return BRW_TYPE_Q;
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
return BRW_REGISTER_TYPE_D;
case BRW_TYPE_D:
case BRW_TYPE_UD:
return BRW_TYPE_D;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_V:
case BRW_REGISTER_TYPE_UV:
return BRW_REGISTER_TYPE_W;
case BRW_TYPE_W:
case BRW_TYPE_UW:
case BRW_TYPE_B:
case BRW_TYPE_UB:
case BRW_TYPE_V:
case BRW_TYPE_UV:
return BRW_TYPE_W;
default:
unreachable("invalid type");
}
@ -485,7 +485,7 @@ execution_type(const struct brw_isa_info *isa, const brw_inst *inst)
src0_exec_type = execution_type_for_type(brw_inst_src0_type(devinfo, inst));
if (num_sources == 1) {
if (src0_exec_type == BRW_REGISTER_TYPE_HF)
if (src0_exec_type == BRW_TYPE_HF)
return dst_exec_type;
return src0_exec_type;
}
@ -494,27 +494,27 @@ execution_type(const struct brw_isa_info *isa, const brw_inst *inst)
if (types_are_mixed_float(src0_exec_type, src1_exec_type) ||
types_are_mixed_float(src0_exec_type, dst_exec_type) ||
types_are_mixed_float(src1_exec_type, dst_exec_type)) {
return BRW_REGISTER_TYPE_F;
return BRW_TYPE_F;
}
if (src0_exec_type == src1_exec_type)
return src0_exec_type;
if (src0_exec_type == BRW_REGISTER_TYPE_Q ||
src1_exec_type == BRW_REGISTER_TYPE_Q)
return BRW_REGISTER_TYPE_Q;
if (src0_exec_type == BRW_TYPE_Q ||
src1_exec_type == BRW_TYPE_Q)
return BRW_TYPE_Q;
if (src0_exec_type == BRW_REGISTER_TYPE_D ||
src1_exec_type == BRW_REGISTER_TYPE_D)
return BRW_REGISTER_TYPE_D;
if (src0_exec_type == BRW_TYPE_D ||
src1_exec_type == BRW_TYPE_D)
return BRW_TYPE_D;
if (src0_exec_type == BRW_REGISTER_TYPE_W ||
src1_exec_type == BRW_REGISTER_TYPE_W)
return BRW_REGISTER_TYPE_W;
if (src0_exec_type == BRW_TYPE_W ||
src1_exec_type == BRW_TYPE_W)
return BRW_TYPE_W;
if (src0_exec_type == BRW_REGISTER_TYPE_DF ||
src1_exec_type == BRW_REGISTER_TYPE_DF)
return BRW_REGISTER_TYPE_DF;
if (src0_exec_type == BRW_TYPE_DF ||
src1_exec_type == BRW_TYPE_DF)
return BRW_TYPE_DF;
unreachable("not reached");
}
@ -568,13 +568,13 @@ is_half_float_conversion(const struct brw_isa_info *isa,
enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
if (dst_type != src0_type &&
(dst_type == BRW_REGISTER_TYPE_HF || src0_type == BRW_REGISTER_TYPE_HF)) {
(dst_type == BRW_TYPE_HF || src0_type == BRW_TYPE_HF)) {
return true;
} else if (num_sources > 1) {
enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst);
return dst_type != src1_type &&
(dst_type == BRW_REGISTER_TYPE_HF ||
src1_type == BRW_REGISTER_TYPE_HF);
(dst_type == BRW_TYPE_HF ||
src1_type == BRW_TYPE_HF);
}
return false;
@ -687,12 +687,12 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
dst_type = inst_dst_type(isa, inst);
}
ERROR_IF(dst_type == BRW_REGISTER_TYPE_DF &&
ERROR_IF(dst_type == BRW_TYPE_DF &&
!devinfo->has_64bit_float,
"64-bit float destination, but platform does not support it");
ERROR_IF((dst_type == BRW_REGISTER_TYPE_Q ||
dst_type == BRW_REGISTER_TYPE_UQ) &&
ERROR_IF((dst_type == BRW_TYPE_Q ||
dst_type == BRW_TYPE_UQ) &&
!devinfo->has_64bit_int,
"64-bit int destination, but platform does not support it");
@ -717,12 +717,12 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
}
}
ERROR_IF(src_type == BRW_REGISTER_TYPE_DF &&
ERROR_IF(src_type == BRW_TYPE_DF &&
!devinfo->has_64bit_float,
"64-bit float source, but platform does not support it");
ERROR_IF((src_type == BRW_REGISTER_TYPE_Q ||
src_type == BRW_REGISTER_TYPE_UQ) &&
ERROR_IF((src_type == BRW_TYPE_Q ||
src_type == BRW_TYPE_UQ) &&
!devinfo->has_64bit_int,
"64-bit int source, but platform does not support it");
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16 &&
@ -768,13 +768,13 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
* value to a vector before using in a HF (packed or unpacked)
* math operation.
*/
ERROR_IF(brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_HF &&
ERROR_IF(brw_inst_src0_type(devinfo, inst) == BRW_TYPE_HF &&
src0_has_scalar_region(devinfo, inst),
"Scalar broadcast on HF math (packed or unpacked) must not "
"be used.");
if (num_sources > 1) {
ERROR_IF(brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_HF &&
ERROR_IF(brw_inst_src1_type(devinfo, inst) == BRW_TYPE_HF &&
src1_has_scalar_region(devinfo, inst),
"Scalar broadcast on HF math (packed or unpacked) must not "
"be used.");
@ -798,8 +798,8 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
bool dst_type_is_byte =
inst_dst_type(isa, inst) == BRW_REGISTER_TYPE_B ||
inst_dst_type(isa, inst) == BRW_REGISTER_TYPE_UB;
inst_dst_type(isa, inst) == BRW_TYPE_B ||
inst_dst_type(isa, inst) == BRW_TYPE_UB;
if (dst_type_is_byte) {
if (is_packed(exec_size * dst_stride, exec_size, dst_stride)) {
@ -854,14 +854,14 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
enum brw_reg_type src1_type = num_sources > 1 ?
brw_inst_src1_type(devinfo, inst) : 0;
ERROR_IF(dst_type == BRW_REGISTER_TYPE_HF &&
ERROR_IF(dst_type == BRW_TYPE_HF &&
(type_sz(src0_type) == 8 ||
(num_sources > 1 && type_sz(src1_type) == 8)),
"There are no direct conversions between 64-bit types and HF");
ERROR_IF(type_sz(dst_type) == 8 &&
(src0_type == BRW_REGISTER_TYPE_HF ||
(num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)),
(src0_type == BRW_TYPE_HF ||
(num_sources > 1 && src1_type == BRW_TYPE_HF)),
"There are no direct conversions between 64-bit types and HF");
/* From the BDW+ PRM:
@ -895,12 +895,12 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
* apply to Align16 mode.
*/
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
if ((dst_type == BRW_REGISTER_TYPE_HF &&
if ((dst_type == BRW_TYPE_HF &&
(brw_reg_type_is_integer(src0_type) ||
(num_sources > 1 && brw_reg_type_is_integer(src1_type)))) ||
(brw_reg_type_is_integer(dst_type) &&
(src0_type == BRW_REGISTER_TYPE_HF ||
(num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)))) {
(src0_type == BRW_TYPE_HF ||
(num_sources > 1 && src1_type == BRW_TYPE_HF)))) {
ERROR_IF(dst_stride * dst_type_size != 4,
"Conversions between integer and half-float must be "
"strided by a DWord on the destination");
@ -909,7 +909,7 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
ERROR_IF(subreg % 4 != 0,
"Conversions between integer and half-float must be "
"aligned to a DWord on the destination");
} else if (dst_type == BRW_REGISTER_TYPE_HF) {
} else if (dst_type == BRW_TYPE_HF) {
unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
ERROR_IF(dst_stride != 2 &&
!(is_mixed_float(isa, inst) &&
@ -1150,7 +1150,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
* execution size must be no more than 8."
*/
ERROR_IF(exec_size > 8 && devinfo->ver < 20 &&
dst_type == BRW_REGISTER_TYPE_F &&
dst_type == BRW_TYPE_F &&
opcode != BRW_OPCODE_MOV,
"Mixed float mode with 32-bit float destination is limited "
"to SIMD8");
@ -1226,7 +1226,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
* Align1 and Align16."
*/
ERROR_IF(exec_size > 8 && dst_is_packed &&
dst_type == BRW_REGISTER_TYPE_HF &&
dst_type == BRW_TYPE_HF &&
opcode != BRW_OPCODE_MOV,
"Align1 mixed float mode is limited to SIMD8 when destination "
"is packed half-float");
@ -1238,18 +1238,18 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
* - In Align1, f16 inputs need to be strided"
*/
if (opcode == BRW_OPCODE_MATH) {
if (src0_type == BRW_REGISTER_TYPE_HF) {
if (src0_type == BRW_TYPE_HF) {
ERROR_IF(STRIDE(brw_inst_src0_hstride(devinfo, inst)) <= 1,
"Align1 mixed mode math needs strided half-float inputs");
}
if (num_sources >= 2 && src1_type == BRW_REGISTER_TYPE_HF) {
if (num_sources >= 2 && src1_type == BRW_TYPE_HF) {
ERROR_IF(STRIDE(brw_inst_src1_hstride(devinfo, inst)) <= 1,
"Align1 mixed mode math needs strided half-float inputs");
}
}
if (dst_type == BRW_REGISTER_TYPE_HF && dst_stride == 1) {
if (dst_type == BRW_TYPE_HF && dst_stride == 1) {
/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
* Float Operations:
*
@ -1284,8 +1284,8 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
* so we only need to check this for Align1.
*/
if (src0_is_acc(devinfo, inst) &&
(src0_type == BRW_REGISTER_TYPE_F ||
src0_type == BRW_REGISTER_TYPE_HF)) {
(src0_type == BRW_TYPE_F ||
src0_type == BRW_TYPE_HF)) {
ERROR_IF(brw_inst_src0_da1_subreg_nr(devinfo, inst) != 0,
"Mixed float mode requires register-aligned accumulator "
"source reads when destination is packed half-float");
@ -1294,8 +1294,8 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
if (num_sources > 1 &&
src1_is_acc(devinfo, inst) &&
(src1_type == BRW_REGISTER_TYPE_F ||
src1_type == BRW_REGISTER_TYPE_HF)) {
(src1_type == BRW_TYPE_F ||
src1_type == BRW_TYPE_HF)) {
ERROR_IF(brw_inst_src1_da1_subreg_nr(devinfo, inst) != 0,
"Mixed float mode requires register-aligned accumulator "
"source reads when destination is packed half-float");
@ -1314,7 +1314,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
* or its link to the implication described after it, so we only
* validate the explicit implication, which is clearly described.
*/
if (dst_type == BRW_REGISTER_TYPE_HF &&
if (dst_type == BRW_TYPE_HF &&
inst_uses_src_acc(isa, inst)) {
ERROR_IF(dst_stride != 2,
"Mixed float mode with implicit/explicit accumulator "
@ -1550,14 +1550,14 @@ vector_immediate_restrictions(const struct brw_isa_info *isa,
* applies.
*/
switch (type) {
case BRW_REGISTER_TYPE_V:
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_VF:
case BRW_TYPE_V:
case BRW_TYPE_UV:
case BRW_TYPE_VF:
ERROR_IF(dst_subreg % (128 / 8) != 0,
"Destination must be 128-bit aligned in order to use immediate "
"vector types");
if (type == BRW_REGISTER_TYPE_VF) {
if (type == BRW_TYPE_VF) {
ERROR_IF(dst_type_size * dst_stride != 4,
"Destination must have stride equivalent to dword in order "
"to use the VF type");
@ -1604,10 +1604,10 @@ special_requirements_for_handling_double_precision_data_types(
bool is_integer_dword_multiply =
brw_inst_opcode(isa, inst) == BRW_OPCODE_MUL &&
(brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UD) &&
(brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_UD);
(brw_inst_src0_type(devinfo, inst) == BRW_TYPE_D ||
brw_inst_src0_type(devinfo, inst) == BRW_TYPE_UD) &&
(brw_inst_src1_type(devinfo, inst) == BRW_TYPE_D ||
brw_inst_src1_type(devinfo, inst) == BRW_TYPE_UD);
const bool is_double_precision =
dst_type_size == 8 || exec_type_size == 8 || is_integer_dword_multiply;
@ -1896,14 +1896,14 @@ instruction_restrictions(const struct brw_isa_info *isa,
* be used." I have interpreted it as the latter primarily because that
* is the more restrictive interpretation.
*/
ERROR_IF((src0_type == BRW_REGISTER_TYPE_UD ||
src0_type == BRW_REGISTER_TYPE_D ||
src1_type == BRW_REGISTER_TYPE_UD ||
src1_type == BRW_REGISTER_TYPE_D) &&
(dst_type == BRW_REGISTER_TYPE_UD ||
dst_type == BRW_REGISTER_TYPE_D ||
dst_type == BRW_REGISTER_TYPE_UW ||
dst_type == BRW_REGISTER_TYPE_W) &&
ERROR_IF((src0_type == BRW_TYPE_UD ||
src0_type == BRW_TYPE_D ||
src1_type == BRW_TYPE_UD ||
src1_type == BRW_TYPE_D) &&
(dst_type == BRW_TYPE_UD ||
dst_type == BRW_TYPE_D ||
dst_type == BRW_TYPE_UW ||
dst_type == BRW_TYPE_W) &&
(brw_inst_saturate(devinfo, inst) != 0 ||
brw_inst_cond_modifier(devinfo, inst) != BRW_CONDITIONAL_NONE),
"Neither Saturate nor conditional modifier allowed with DW "
@ -1948,10 +1948,10 @@ instruction_restrictions(const struct brw_isa_info *isa,
if (brw_inst_opcode(isa, inst) == BRW_OPCODE_ADD3) {
const enum brw_reg_type dst_type = inst_dst_type(isa, inst);
ERROR_IF(dst_type != BRW_REGISTER_TYPE_D &&
dst_type != BRW_REGISTER_TYPE_UD &&
dst_type != BRW_REGISTER_TYPE_W &&
dst_type != BRW_REGISTER_TYPE_UW,
ERROR_IF(dst_type != BRW_TYPE_D &&
dst_type != BRW_TYPE_UD &&
dst_type != BRW_TYPE_W &&
dst_type != BRW_TYPE_UW,
"Destination must be integer D, UD, W, or UW type.");
for (unsigned i = 0; i < 3; i++) {
@ -1964,22 +1964,22 @@ instruction_restrictions(const struct brw_isa_info *isa,
default: unreachable("invalid src");
}
ERROR_IF(src_type != BRW_REGISTER_TYPE_D &&
src_type != BRW_REGISTER_TYPE_UD &&
src_type != BRW_REGISTER_TYPE_W &&
src_type != BRW_REGISTER_TYPE_UW,
ERROR_IF(src_type != BRW_TYPE_D &&
src_type != BRW_TYPE_UD &&
src_type != BRW_TYPE_W &&
src_type != BRW_TYPE_UW,
"Source must be integer D, UD, W, or UW type.");
if (i == 0) {
if (brw_inst_3src_a1_src0_is_imm(devinfo, inst)) {
ERROR_IF(src_type != BRW_REGISTER_TYPE_W &&
src_type != BRW_REGISTER_TYPE_UW,
ERROR_IF(src_type != BRW_TYPE_W &&
src_type != BRW_TYPE_UW,
"Immediate source must be integer W or UW type.");
}
} else if (i == 2) {
if (brw_inst_3src_a1_src2_is_imm(devinfo, inst)) {
ERROR_IF(src_type != BRW_REGISTER_TYPE_W &&
src_type != BRW_REGISTER_TYPE_UW,
ERROR_IF(src_type != BRW_TYPE_W &&
src_type != BRW_TYPE_UW,
"Immediate source must be integer W or UW type.");
}
}
@ -2051,8 +2051,8 @@ instruction_restrictions(const struct brw_isa_info *isa,
else
dst_type = brw_inst_3src_a16_dst_type(devinfo, inst);
ERROR_IF(dst_type != BRW_REGISTER_TYPE_D &&
dst_type != BRW_REGISTER_TYPE_UD,
ERROR_IF(dst_type != BRW_TYPE_D &&
dst_type != BRW_TYPE_UD,
"BFI2 destination type must be D or UD");
for (unsigned s = 0; s < 3; s++) {
@ -2092,13 +2092,13 @@ instruction_restrictions(const struct brw_isa_info *isa,
dst_type = brw_inst_3src_a16_dst_type(devinfo, inst);
if (devinfo->ver == 9) {
ERROR_IF(dst_type != BRW_REGISTER_TYPE_F,
ERROR_IF(dst_type != BRW_TYPE_F,
"CSEL destination type must be F");
} else {
ERROR_IF(dst_type != BRW_REGISTER_TYPE_F &&
dst_type != BRW_REGISTER_TYPE_HF &&
dst_type != BRW_REGISTER_TYPE_D &&
dst_type != BRW_REGISTER_TYPE_W,
ERROR_IF(dst_type != BRW_TYPE_F &&
dst_type != BRW_TYPE_HF &&
dst_type != BRW_TYPE_D &&
dst_type != BRW_TYPE_W,
"CSEL destination type must be F, HF, D, or W");
}
@ -2139,7 +2139,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
const enum gfx12_sub_byte_precision src1_sub_byte =
brw_inst_dpas_3src_src1_subbyte(devinfo, inst);
if (src1_type != BRW_REGISTER_TYPE_B && src1_type != BRW_REGISTER_TYPE_UB) {
if (src1_type != BRW_TYPE_B && src1_type != BRW_TYPE_UB) {
ERROR_IF(src1_sub_byte != BRW_SUB_BYTE_PRECISION_NONE,
"Sub-byte precision must be None for source type larger than Byte.");
} else {
@ -2152,7 +2152,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
const enum gfx12_sub_byte_precision src2_sub_byte =
brw_inst_dpas_3src_src2_subbyte(devinfo, inst);
if (src2_type != BRW_REGISTER_TYPE_B && src2_type != BRW_REGISTER_TYPE_UB) {
if (src2_type != BRW_TYPE_B && src2_type != BRW_TYPE_UB) {
ERROR_IF(src2_sub_byte != BRW_SUB_BYTE_PRECISION_NONE,
"Sub-byte precision must be None.");
} else {
@ -2231,26 +2231,26 @@ instruction_restrictions(const struct brw_isa_info *isa,
if (brw_inst_dpas_3src_exec_type(devinfo, inst) ==
BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT) {
ERROR_IF(dst_type != BRW_REGISTER_TYPE_F,
ERROR_IF(dst_type != BRW_TYPE_F,
"DPAS destination type must be F.");
ERROR_IF(src0_type != BRW_REGISTER_TYPE_F,
ERROR_IF(src0_type != BRW_TYPE_F,
"DPAS src0 type must be F.");
ERROR_IF(src1_type != BRW_REGISTER_TYPE_HF,
ERROR_IF(src1_type != BRW_TYPE_HF,
"DPAS src1 type must be HF.");
ERROR_IF(src2_type != BRW_REGISTER_TYPE_HF,
ERROR_IF(src2_type != BRW_TYPE_HF,
"DPAS src2 type must be HF.");
} else {
ERROR_IF(dst_type != BRW_REGISTER_TYPE_D &&
dst_type != BRW_REGISTER_TYPE_UD,
ERROR_IF(dst_type != BRW_TYPE_D &&
dst_type != BRW_TYPE_UD,
"DPAS destination type must be D or UD.");
ERROR_IF(src0_type != BRW_REGISTER_TYPE_D &&
src0_type != BRW_REGISTER_TYPE_UD,
ERROR_IF(src0_type != BRW_TYPE_D &&
src0_type != BRW_TYPE_UD,
"DPAS src0 type must be D or UD.");
ERROR_IF(src1_type != BRW_REGISTER_TYPE_B &&
src1_type != BRW_REGISTER_TYPE_UB,
ERROR_IF(src1_type != BRW_TYPE_B &&
src1_type != BRW_TYPE_UB,
"DPAS src1 base type must be B or UB.");
ERROR_IF(src2_type != BRW_REGISTER_TYPE_B &&
src2_type != BRW_REGISTER_TYPE_UB,
ERROR_IF(src2_type != BRW_TYPE_B &&
src2_type != BRW_TYPE_UB,
"DPAS src2 base type must be B or UB.");
if (brw_reg_type_is_unsigned_integer(dst_type)) {

108
src/intel/compiler/brw_fs.cpp
View file

@ -218,7 +218,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
* be any component of a vector, and then we load 4 contiguous
* components starting from that. TODO: Support loading fewer than 4.
*/
fs_reg total_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg total_offset = bld.vgrf(BRW_TYPE_UD);
bld.ADD(total_offset, varying_offset, brw_imm_ud(const_offset));
/* The pull load message will load a vec4 (16 bytes). If we are loading
@ -227,7 +227,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
* so other parts of the driver don't get confused about the size of the
* result.
*/
fs_reg vec4_result = bld.vgrf(BRW_REGISTER_TYPE_F, 4);
fs_reg vec4_result = bld.vgrf(BRW_TYPE_F, 4);
fs_reg srcs[PULL_VARYING_CONSTANT_SRCS];
srcs[PULL_VARYING_CONSTANT_SRC_SURFACE] = surface;
@ -410,10 +410,10 @@ fs_inst::has_source_and_destination_hazard() const
if (exec_size == 16) {
for (int i = 0; i < sources; i++) {
if (src[i].file == VGRF && (src[i].stride == 0 ||
src[i].type == BRW_REGISTER_TYPE_UW ||
src[i].type == BRW_REGISTER_TYPE_W ||
src[i].type == BRW_REGISTER_TYPE_UB ||
src[i].type == BRW_REGISTER_TYPE_B)) {
src[i].type == BRW_TYPE_UW ||
src[i].type == BRW_TYPE_W ||
src[i].type == BRW_TYPE_UB ||
src[i].type == BRW_TYPE_B)) {
return true;
}
}
@ -545,7 +545,7 @@ void
fs_reg::init()
{
memset((void*)this, 0, sizeof(*this));
type = BRW_REGISTER_TYPE_UD;
type = BRW_TYPE_UD;
stride = 1;
}
@ -562,9 +562,9 @@ fs_reg::fs_reg(struct ::brw_reg reg) :
this->offset = 0;
this->stride = 1;
if (this->file == IMM &&
(this->type != BRW_REGISTER_TYPE_V &&
this->type != BRW_REGISTER_TYPE_UV &&
this->type != BRW_REGISTER_TYPE_VF)) {
(this->type != BRW_TYPE_V &&
this->type != BRW_TYPE_UV &&
this->type != BRW_TYPE_VF)) {
this->stride = 0;
}
}
@ -700,7 +700,7 @@ fs_inst::is_partial_write() const
/* Special case UNDEF since a lot of places in the backend do things like this :
*
* fs_builder ubld = bld.exec_all().group(1, 0);
* fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD);
* fs_reg tmp = ubld.vgrf(BRW_TYPE_UD);
* ubld.UNDEF(tmp); <- partial write, even if the whole register is concerned
*/
if (this->opcode == SHADER_OPCODE_UNDEF) {
@ -923,7 +923,7 @@ fs_inst::size_read(int arg) const
case SHADER_OPCODE_LOAD_PAYLOAD:
if (arg < this->header_size)
return retype(src[arg], BRW_REGISTER_TYPE_UD).component_size(8);
return retype(src[arg], BRW_TYPE_UD).component_size(8);
break;
case SHADER_OPCODE_BARRIER:
@ -939,7 +939,7 @@ fs_inst::size_read(int arg) const
case BRW_OPCODE_DPAS:
switch (arg) {
case 0:
if (src[0].type == BRW_REGISTER_TYPE_HF) {
if (src[0].type == BRW_TYPE_HF) {
return rcount * REG_SIZE / 2;
} else {
return rcount * REG_SIZE;
@ -1067,7 +1067,7 @@ fs_reg::fs_reg(enum brw_reg_file file, unsigned nr)
init();
this->file = file;
this->nr = nr;
this->type = BRW_REGISTER_TYPE_F;
this->type = BRW_TYPE_F;
this->stride = (file == UNIFORM ? 0 : 1);
}
@ -1243,9 +1243,9 @@ fs_visitor::assign_curb_setup()
/* The base offset for our push data is passed in as R0.0[31:6]. We have
* to mask off the bottom 6 bits.
*/
fs_reg base_addr = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg base_addr = ubld.vgrf(BRW_TYPE_UD);
ubld.AND(base_addr,
retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 0), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 6)));
/* On Gfx12-HP we load constants at the start of the program using A32
@ -1263,7 +1263,7 @@ fs_visitor::assign_curb_setup()
* emit an 'ADD addr, base_addr, 0' instruction.
*/
if (i != 0) {
addr = ubld.vgrf(BRW_REGISTER_TYPE_UD);
addr = ubld.vgrf(BRW_TYPE_UD);
ubld.ADD(addr, base_addr, brw_imm_ud(i * REG_SIZE));
} else {
addr = base_addr;
@ -1277,7 +1277,7 @@ fs_visitor::assign_curb_setup()
};
fs_reg dest = retype(brw_vec8_grf(payload().num_regs + i, 0),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
fs_inst *send = ubld.emit(SHADER_OPCODE_SEND, dest, srcs, 4);
send->sfid = GFX12_SFID_UGM;
@ -1351,14 +1351,14 @@ fs_visitor::assign_curb_setup()
fs_reg b32;
for (unsigned i = 0; i < 64; i++) {
if (i % 16 == 0 && (want_zero & BITFIELD64_RANGE(i, 16))) {
fs_reg shifted = ubld.vgrf(BRW_REGISTER_TYPE_W, 2);
fs_reg shifted = ubld.vgrf(BRW_TYPE_W, 2);
ubld.SHL(horiz_offset(shifted, 8),
byte_offset(retype(mask, BRW_REGISTER_TYPE_W), i / 8),
byte_offset(retype(mask, BRW_TYPE_W), i / 8),
brw_imm_v(0x01234567));
ubld.SHL(shifted, horiz_offset(shifted, 8), brw_imm_w(8));
fs_builder ubld16 = ubld.group(16, 0);
b32 = ubld16.vgrf(BRW_REGISTER_TYPE_D);
b32 = ubld16.vgrf(BRW_TYPE_D);
ubld16.group(16, 0).ASR(b32, shifted, brw_imm_w(15));
}
@ -1366,7 +1366,7 @@ fs_visitor::assign_curb_setup()
assert(i < prog_data->curb_read_length);
struct brw_reg push_reg =
retype(brw_vec8_grf(payload().num_regs + i, 0),
BRW_REGISTER_TYPE_D);
BRW_TYPE_D);
ubld.AND(push_reg, push_reg, component(b32, i % 16));
}
@ -2032,12 +2032,12 @@ fs_visitor::emit_repclear_shader()
assert(uniforms == 0);
assume(key->nr_color_regions > 0);
fs_reg color_output = retype(brw_vec4_grf(127, 0), BRW_REGISTER_TYPE_UD);
fs_reg header = retype(brw_vec8_grf(125, 0), BRW_REGISTER_TYPE_UD);
fs_reg color_output = retype(brw_vec4_grf(127, 0), BRW_TYPE_UD);
fs_reg header = retype(brw_vec8_grf(125, 0), BRW_TYPE_UD);
/* We pass the clear color as a flat input. Copy it to the output. */
fs_reg color_input =
brw_reg(BRW_GENERAL_REGISTER_FILE, 2, 3, 0, 0, BRW_REGISTER_TYPE_UD,
brw_reg(BRW_GENERAL_REGISTER_FILE, 2, 3, 0, 0, BRW_TYPE_UD,
BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
@ -2047,7 +2047,7 @@ fs_visitor::emit_repclear_shader()
if (key->nr_color_regions > 1) {
/* Copy g0..g1 as the message header */
bld.exec_all().group(16, 0)
.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
.MOV(header, retype(brw_vec8_grf(0, 0), BRW_TYPE_UD));
}
for (int i = 0; i < key->nr_color_regions; ++i) {
@ -2100,7 +2100,7 @@ brw_sample_mask_reg(const fs_builder &bld)
assert(bld.dispatch_width() <= 16);
assert(s.devinfo->ver < 20);
return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7),
BRW_REGISTER_TYPE_UW);
BRW_TYPE_UW);
}
}
@ -2591,40 +2591,40 @@ fs_visitor::dump_instruction_to_file(const fs_inst *inst, FILE *file) const
break;
case IMM:
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
fprintf(file, "%-ghf", _mesa_half_to_float(inst->src[i].ud & 0xffff));
break;
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
fprintf(file, "%-gf", inst->src[i].f);
break;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
fprintf(file, "%fdf", inst->src[i].df);
break;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_W:
case BRW_TYPE_D:
fprintf(file, "%dd", inst->src[i].d);
break;
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_UW:
case BRW_TYPE_UD:
fprintf(file, "%uu", inst->src[i].ud);
break;
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_Q:
fprintf(file, "%" PRId64 "q", inst->src[i].d64);
break;
case BRW_REGISTER_TYPE_UQ:
case BRW_TYPE_UQ:
fprintf(file, "%" PRIu64 "uq", inst->src[i].u64);
break;
case BRW_REGISTER_TYPE_VF:
case BRW_TYPE_VF:
fprintf(file, "[%-gF, %-gF, %-gF, %-gF]",
brw_vf_to_float((inst->src[i].ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 24) & 0xff));
break;
case BRW_REGISTER_TYPE_V:
case BRW_REGISTER_TYPE_UV:
case BRW_TYPE_V:
case BRW_TYPE_UV:
fprintf(file, "%08x%s", inst->src[i].ud,
inst->src[i].type == BRW_REGISTER_TYPE_V ? "V" : "UV");
inst->src[i].type == BRW_TYPE_V ? "V" : "UV");
break;
default:
fprintf(file, "???");
@ -3027,11 +3027,11 @@ fs_visitor::set_tcs_invocation_id()
* * 22:16 on gfx11+
* * 23:17 otherwise
*/
fs_reg t = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.AND(t, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)),
fs_reg t = bld.vgrf(BRW_TYPE_UD);
bld.AND(t, fs_reg(retype(brw_vec1_grf(0, 2), BRW_TYPE_UD)),
brw_imm_ud(instance_id_mask));
invocation_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
invocation_id = bld.vgrf(BRW_TYPE_UD);
if (vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH) {
/* gl_InvocationID is just the thread number */
@ -3041,15 +3041,15 @@ fs_visitor::set_tcs_invocation_id()
assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH);
fs_reg channels_uw = bld.vgrf(BRW_REGISTER_TYPE_UW);
fs_reg channels_ud = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg channels_uw = bld.vgrf(BRW_TYPE_UW);
fs_reg channels_ud = bld.vgrf(BRW_TYPE_UD);
bld.MOV(channels_uw, fs_reg(brw_imm_uv(0x76543210)));
bld.MOV(channels_ud, channels_uw);
if (tcs_prog_data->instances == 1) {
invocation_id = channels_ud;
} else {
fs_reg instance_times_8 = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg instance_times_8 = bld.vgrf(BRW_TYPE_UD);
bld.SHR(instance_times_8, t, brw_imm_ud(instance_id_shift - 3));
bld.ADD(invocation_id, instance_times_8, channels_ud);
}
@ -3175,11 +3175,11 @@ fs_visitor::run_gs()
const fs_builder bld = fs_builder(this).at_end();
this->final_gs_vertex_count = bld.vgrf(BRW_REGISTER_TYPE_UD);
this->final_gs_vertex_count = bld.vgrf(BRW_TYPE_UD);
if (gs_compile->control_data_header_size_bits > 0) {
/* Create a VGRF to store accumulated control data bits. */
this->control_data_bits = bld.vgrf(BRW_REGISTER_TYPE_UD);
this->control_data_bits = bld.vgrf(BRW_TYPE_UD);
/* If we're outputting more than 32 control data bits, then EmitVertex()
* will set control_data_bits to 0 after emitting the first vertex.
@ -3281,7 +3281,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
brw_vec1_grf(i + 1, 7);
bld.exec_all().group(1, 0)
.MOV(brw_sample_mask_reg(bld.group(lower_width, i)),
retype(dispatch_mask, BRW_REGISTER_TYPE_UW));
retype(dispatch_mask, BRW_TYPE_UW));
}
}
@ -3327,8 +3327,8 @@ fs_visitor::run_cs(bool allow_spilling)
if (devinfo->platform == INTEL_PLATFORM_HSW && prog_data->total_shared > 0) {
/* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
const fs_builder abld = bld.exec_all().group(1, 0);
abld.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW),
suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW), 1));
abld.MOV(retype(brw_sr0_reg(1), BRW_TYPE_UW),
suboffset(retype(brw_vec1_grf(0, 0), BRW_TYPE_UW), 1));
}
nir_to_brw(this);
@ -4517,7 +4517,7 @@ brw_fs_test_dispatch_packing(const fs_builder &bld)
shader->max_polygons,
shader->prog_data)) {
const fs_builder ubld = bld.exec_all().group(1, 0);
const fs_reg tmp = component(bld.vgrf(BRW_REGISTER_TYPE_UD), 0);
const fs_reg tmp = component(bld.vgrf(BRW_TYPE_UD), 0);
const fs_reg mask = uses_vmask ? brw_vmask_reg() : brw_dmask_reg();
ubld.ADD(tmp, mask, brw_imm_ud(1));
@ -4581,9 +4581,9 @@ namespace brw {
if (!regs[0])
return fs_reg();
else if (bld.shader->devinfo->ver >= 20)
return fetch_payload_reg(bld, regs, BRW_REGISTER_TYPE_F, 2);
return fetch_payload_reg(bld, regs, BRW_TYPE_F, 2);
const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
const fs_reg tmp = bld.vgrf(BRW_TYPE_F, 2);
const brw::fs_builder hbld = bld.exec_all().group(8, 0);
const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
fs_reg *const components = new fs_reg[2 * m];

4
src/intel/compiler/brw_fs.h
View file

@ -538,7 +538,7 @@ private:
namespace brw {
fs_reg
fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2],
brw_reg_type type = BRW_REGISTER_TYPE_F,
brw_reg_type type = BRW_TYPE_F,
unsigned n = 1);
fs_reg
@ -548,7 +548,7 @@ namespace brw {
dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data)
{
return fs_reg(UNIFORM, wm_prog_data->msaa_flags_param,
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
}
void

40
src/intel/compiler/brw_fs_builder.h
View file

@ -205,13 +205,13 @@ namespace brw {
fs_reg
null_reg_f() const
{
return fs_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
return fs_reg(retype(brw_null_reg(), BRW_TYPE_F));
}
fs_reg
null_reg_df() const
{
return fs_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF));
return fs_reg(retype(brw_null_reg(), BRW_TYPE_DF));
}
/**
@ -220,7 +220,7 @@ namespace brw {
fs_reg
null_reg_d() const
{
return fs_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
return fs_reg(retype(brw_null_reg(), BRW_TYPE_D));
}
/**
@ -229,7 +229,7 @@ namespace brw {
fs_reg
null_reg_ud() const
{
return fs_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
return fs_reg(retype(brw_null_reg(), BRW_TYPE_UD));
}
/**
@ -378,7 +378,7 @@ namespace brw {
* should go back to scalar destinations here.
*/
const fs_builder ubld = exec_all();
const fs_reg chan_index = vgrf(BRW_REGISTER_TYPE_UD);
const fs_reg chan_index = vgrf(BRW_TYPE_UD);
const fs_reg dst = vgrf(src.type);
ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
@ -411,8 +411,8 @@ namespace brw {
fs_reg left, right;
left = horiz_stride(horiz_offset(tmp, left_offset), left_stride);
right = horiz_stride(horiz_offset(tmp, right_offset), right_stride);
if ((tmp.type == BRW_REGISTER_TYPE_Q ||
tmp.type == BRW_REGISTER_TYPE_UQ) &&
if ((tmp.type == BRW_TYPE_Q ||
tmp.type == BRW_TYPE_UQ) &&
!shader->devinfo->has_64bit_int) {
switch (opcode) {
case BRW_OPCODE_MUL:
@ -431,8 +431,8 @@ namespace brw {
/* We treat the bottom 32 bits as unsigned regardless of
* whether or not the integer as a whole is signed.
*/
fs_reg right_low = subscript(right, BRW_REGISTER_TYPE_UD, 0);
fs_reg left_low = subscript(left, BRW_REGISTER_TYPE_UD, 0);
fs_reg right_low = subscript(right, BRW_TYPE_UD, 0);
fs_reg left_low = subscript(left, BRW_TYPE_UD, 0);
/* The upper bits get the same sign as the 64-bit type */
brw_reg_type type32 = brw_reg_type_from_bit_size(32, tmp.type);
@ -443,8 +443,8 @@ namespace brw {
*
* l_hi < r_hi || (l_hi == r_hi && l_low < r_low)
*/
CMP(null_reg_ud(), retype(left_low, BRW_REGISTER_TYPE_UD),
retype(right_low, BRW_REGISTER_TYPE_UD), mod);
CMP(null_reg_ud(), retype(left_low, BRW_TYPE_UD),
retype(right_low, BRW_TYPE_UD), mod);
set_predicate(BRW_PREDICATE_NORMAL,
CMP(null_reg_ud(), left_high, right_high,
BRW_CONDITIONAL_EQ));
@ -536,7 +536,7 @@ namespace brw {
{
assert(old_inst->dst.file == VGRF);
fs_inst *inst = emit(SHADER_OPCODE_UNDEF,
retype(old_inst->dst, BRW_REGISTER_TYPE_UD));
retype(old_inst->dst, BRW_TYPE_UD));
inst->size_written = old_inst->size_written;
return inst;
@ -701,13 +701,13 @@ namespace brw {
* comparisons. Zero/non-zero (== and !=) comparisons almost work.
* 0x80000000 fails because it is -0.0, and -0.0 == 0.0.
*/
assert(src2.type == BRW_REGISTER_TYPE_F);
assert(src2.type == BRW_TYPE_F);
return set_condmod(condition,
emit(BRW_OPCODE_CSEL,
retype(dst, BRW_REGISTER_TYPE_F),
retype(src0, BRW_REGISTER_TYPE_F),
retype(src1, BRW_REGISTER_TYPE_F),
retype(dst, BRW_TYPE_F),
retype(src0, BRW_TYPE_F),
retype(src1, BRW_TYPE_F),
src2));
}
@ -767,7 +767,7 @@ namespace brw {
assert(dst.file == VGRF);
assert(dst.offset % REG_SIZE == 0);
fs_inst *inst = emit(SHADER_OPCODE_UNDEF,
retype(dst, BRW_REGISTER_TYPE_UD));
retype(dst, BRW_TYPE_UD));
inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE - dst.offset;
return inst;
@ -785,7 +785,7 @@ namespace brw {
inst->sdepth = sdepth;
inst->rcount = rcount;
if (dst.type == BRW_REGISTER_TYPE_HF) {
if (dst.type == BRW_TYPE_HF) {
inst->size_written = rcount * REG_SIZE / 2;
} else {
inst->size_written = rcount * REG_SIZE;
@ -811,9 +811,9 @@ namespace brw {
fs_reg
fix_unsigned_negate(const fs_reg &src) const
{
if (src.type == BRW_REGISTER_TYPE_UD &&
if (src.type == BRW_TYPE_UD &&
src.negate) {
fs_reg temp = vgrf(BRW_REGISTER_TYPE_UD);
fs_reg temp = vgrf(BRW_TYPE_UD);
MOV(temp, src);
return fs_reg(temp);
} else {

4
src/intel/compiler/brw_fs_cmod_propagation.cpp
View file

@ -443,9 +443,9 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
if (scan_inst->opcode == BRW_OPCODE_CMP) {
if ((inst->conditional_mod == BRW_CONDITIONAL_NZ) ||
(inst->conditional_mod == BRW_CONDITIONAL_G &&
inst->src[0].type == BRW_REGISTER_TYPE_UD) ||
inst->src[0].type == BRW_TYPE_UD) ||
(inst->conditional_mod == BRW_CONDITIONAL_L &&
inst->src[0].type == BRW_REGISTER_TYPE_D)) {
inst->src[0].type == BRW_TYPE_D)) {
inst->remove(block, true);
progress = true;
break;

70
src/intel/compiler/brw_fs_combine_constants.cpp
View file

@ -1004,7 +1004,7 @@ supports_src_as_imm(const struct intel_device_info *devinfo, const fs_inst *inst
* sizes on Gfx12. On Gfx12.5, floating point sources must all be HF or
* all be F.
*/
return devinfo->verx10 < 125 || inst->src[0].type != BRW_REGISTER_TYPE_F;
return devinfo->verx10 < 125 || inst->src[0].type != BRW_TYPE_F;
default:
return false;
@ -1032,15 +1032,15 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
* since HF/F mixed mode has been removed from the hardware.
*/
switch (inst->src[src_idx].type) {
case BRW_REGISTER_TYPE_F: {
case BRW_TYPE_F: {
uint16_t hf;
if (representable_as_hf(inst->src[src_idx].f, &hf)) {
inst->src[src_idx] = retype(brw_imm_uw(hf), BRW_REGISTER_TYPE_HF);
inst->src[src_idx] = retype(brw_imm_uw(hf), BRW_TYPE_HF);
can_promote = true;
}
break;
}
case BRW_REGISTER_TYPE_D: {
case BRW_TYPE_D: {
int16_t w;
if (representable_as_w(inst->src[src_idx].d, &w)) {
inst->src[src_idx] = brw_imm_w(w);
@ -1048,7 +1048,7 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
}
break;
}
case BRW_REGISTER_TYPE_UD: {
case BRW_TYPE_UD: {
uint16_t uw;
if (representable_as_uw(inst->src[src_idx].ud, &uw)) {
inst->src[src_idx] = brw_imm_uw(uw);
@ -1056,9 +1056,9 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
}
break;
}
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_W:
case BRW_TYPE_UW:
case BRW_TYPE_HF:
can_promote = true;
break;
default:
@ -1096,26 +1096,26 @@ add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip,
brw_reg_type_is_unsigned_integer(inst->src[i].type));
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_DF:
case BRW_TYPE_F:
case BRW_TYPE_HF:
v->type = float_only;
break;
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_UQ:
case BRW_TYPE_Q:
case BRW_TYPE_UD:
case BRW_TYPE_D:
case BRW_TYPE_UW:
case BRW_TYPE_W:
v->type = integer_only;
break;
case BRW_REGISTER_TYPE_VF:
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_V:
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case BRW_TYPE_VF:
case BRW_TYPE_UV:
case BRW_TYPE_V:
case BRW_TYPE_UB:
case BRW_TYPE_B:
default:
unreachable("not reached");
}
@ -1455,7 +1455,7 @@ brw_fs_opt_combine_constants(fs_visitor &s)
imm->block = intersection;
}
if (ib->inst->src[src].type == BRW_REGISTER_TYPE_HF)
if (ib->inst->src[src].type == BRW_TYPE_HF)
imm->is_half_float = true;
}
@ -1591,13 +1591,13 @@ brw_fs_opt_combine_constants(fs_visitor &s)
switch (type_sz(reg->type)) {
case 2:
reg->type = BRW_REGISTER_TYPE_HF;
reg->type = BRW_TYPE_HF;
break;
case 4:
reg->type = BRW_REGISTER_TYPE_F;
reg->type = BRW_TYPE_F;
break;
case 8:
reg->type = BRW_REGISTER_TYPE_DF;
reg->type = BRW_TYPE_DF;
break;
default:
unreachable("Bad type size");
@ -1611,38 +1611,38 @@ brw_fs_opt_combine_constants(fs_visitor &s)
#if MESA_DEBUG
switch (reg->type) {
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
assert((isnan(reg->df) && isnan(table.imm[i].df)) ||
(fabs(reg->df) == fabs(table.imm[i].df)));
break;
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
assert((isnan(reg->f) && isnan(table.imm[i].f)) ||
(fabsf(reg->f) == fabsf(table.imm[i].f)));
break;
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
assert((isnan(_mesa_half_to_float(reg->d & 0xffffu)) &&
isnan(_mesa_half_to_float(table.imm[i].w))) ||
(fabsf(_mesa_half_to_float(reg->d & 0xffffu)) ==
fabsf(_mesa_half_to_float(table.imm[i].w))));
break;
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_Q:
assert(abs(reg->d64) == abs(table.imm[i].d64));
break;
case BRW_REGISTER_TYPE_UQ:
case BRW_TYPE_UQ:
assert(!link->negate);
assert(reg->d64 == table.imm[i].d64);
break;
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
assert(abs(reg->d) == abs(table.imm[i].d));
break;
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_UD:
assert(!link->negate);
assert(reg->d == table.imm[i].d);
break;
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_W:
assert(abs((int16_t) (reg->d & 0xffff)) == table.imm[i].w);
break;
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_UW:
assert(!link->negate);
assert((reg->ud & 0xffffu) == (uint16_t) table.imm[i].w);
break;

18
src/intel/compiler/brw_fs_copy_propagation.cpp
View file

@ -623,7 +623,7 @@ can_take_stride(fs_inst *inst, brw_reg_type dst_type,
* Prevent copy propagating a scalar value into a math instruction.
*/
if (intel_needs_workaround(devinfo, 22016140776) &&
stride == 0 && inst->src[arg].type == BRW_REGISTER_TYPE_HF) {
stride == 0 && inst->src[arg].type == BRW_TYPE_HF) {
return false;
}
@ -729,7 +729,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
* instead. See also resolve_ud_negate() and comment in
* fs_generator::generate_code.
*/
if (entry->src.type == BRW_REGISTER_TYPE_UD &&
if (entry->src.type == BRW_TYPE_UD &&
entry->src.negate)
return false;
@ -1060,10 +1060,10 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
*/
if (inst->opcode == BRW_OPCODE_MUL &&
type_sz(inst->src[1].type) < 4 &&
(inst->src[0].type == BRW_REGISTER_TYPE_D ||
inst->src[0].type == BRW_REGISTER_TYPE_UD)) {
(inst->src[0].type == BRW_TYPE_D ||
inst->src[0].type == BRW_TYPE_UD)) {
inst->src[0] = val;
inst->src[0].type = BRW_REGISTER_TYPE_D;
inst->src[0].type = BRW_TYPE_D;
progress = true;
break;
}
@ -1082,8 +1082,8 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
if (((inst->opcode == BRW_OPCODE_MUL &&
inst->dst.is_accumulator()) ||
inst->opcode == BRW_OPCODE_MACH) &&
(inst->src[1].type == BRW_REGISTER_TYPE_D ||
inst->src[1].type == BRW_REGISTER_TYPE_UD))
(inst->src[1].type == BRW_TYPE_D ||
inst->src[1].type == BRW_TYPE_UD))
break;
inst->src[0] = inst->src[1];
inst->src[1] = val;
@ -1095,7 +1095,7 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
/* add3 can have a single imm16 source. Proceed if the source type is
* already W or UW or the value can be coerced to one of those types.
*/
if (val.type == BRW_REGISTER_TYPE_W || val.type == BRW_REGISTER_TYPE_UW)
if (val.type == BRW_TYPE_W || val.type == BRW_TYPE_UW)
; /* Nothing to do. */
else if (val.ud <= 0xffff)
val = brw_imm_uw(val.ud);
@ -1358,7 +1358,7 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx,
(inst->src[i].file == FIXED_GRF &&
inst->src[i].is_contiguous())) {
const brw_reg_type t = i < inst->header_size ?
BRW_REGISTER_TYPE_UD : inst->src[i].type;
BRW_TYPE_UD : inst->src[i].type;
fs_reg dst = byte_offset(retype(inst->dst, t), offset);
if (!dst.equals(inst->src[i])) {
acp_entry *entry = linear_zalloc(lin_ctx, acp_entry);

4
src/intel/compiler/brw_fs_cse.cpp
View file

@ -128,7 +128,7 @@ operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
return xs[0].equals(ys[0]) &&
((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
(xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
} else if (a->opcode == BRW_OPCODE_MUL && a->dst.type == BRW_REGISTER_TYPE_F) {
} else if (a->opcode == BRW_OPCODE_MUL && a->dst.type == BRW_TYPE_F) {
bool xs0_negate = xs[0].negate;
bool xs1_negate = xs[1].file == IMM ? xs[1].f < 0.0f
: xs[1].negate;
@ -278,7 +278,7 @@ brw_fs_opt_cse_local(fs_visitor &s, const fs_live_variables &live, bblock_t *blo
if (inst->opcode != BRW_OPCODE_MOV ||
(inst->opcode == BRW_OPCODE_MOV &&
inst->src[0].file == IMM &&
inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
inst->src[0].type == BRW_TYPE_VF)) {
/* Our first sighting of this expression. Create an entry. */
aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
entry->tmp = reg_undef;

68
src/intel/compiler/brw_fs_generator.cpp
View file

@ -201,7 +201,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
struct brw_reg reg,
struct brw_reg indirect_byte_offset)
{
assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
assert(indirect_byte_offset.type == BRW_TYPE_UD);
assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
assert(!reg.abs && !reg.negate);
@ -215,7 +215,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
*/
assert(reg.type == dst.type);
reg.type = dst.type = brw_reg_type_from_bit_size(type_sz(reg.type) * 8,
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
@ -225,11 +225,11 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
reg.nr = imm_byte_offset / REG_SIZE;
reg.subnr = imm_byte_offset % REG_SIZE;
if (type_sz(reg.type) > 4 && !devinfo->has_64bit_int) {
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
subscript(reg, BRW_REGISTER_TYPE_D, 0));
brw_MOV(p, subscript(dst, BRW_TYPE_D, 0),
subscript(reg, BRW_TYPE_D, 0));
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
subscript(reg, BRW_REGISTER_TYPE_D, 1));
brw_MOV(p, subscript(dst, BRW_TYPE_D, 1),
subscript(reg, BRW_TYPE_D, 1));
} else {
brw_MOV(p, dst, reg);
}
@ -250,7 +250,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
* In order to get around this, re retype to UW and use a stride.
*/
indirect_byte_offset =
retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
retype(spread(indirect_byte_offset, 2), BRW_TYPE_UW);
/* There are a number of reasons why we don't use the base offset here.
* One reason is that the field is only 9 bits which means we can only
@ -313,11 +313,11 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
* the indirect here to handle adding 4 bytes to the offset and
* avoid the extra ADD to the register file.
*/
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
brw_MOV(p, subscript(dst, BRW_TYPE_D, 0),
retype(brw_VxH_indirect(0, 0), BRW_TYPE_D));
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
brw_MOV(p, subscript(dst, BRW_TYPE_D, 1),
retype(brw_VxH_indirect(0, 4), BRW_TYPE_D));
} else {
struct brw_reg ind_src = brw_VxH_indirect(0, 0);
@ -350,7 +350,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
*/
assert(src.type == dst.type);
src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8,
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
/* Because we're using the address register, we're limited to 16-wide
* by the address register file and 8-wide for 64-bit types. We could try
@ -396,7 +396,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
* can't use a D-type instruction. In order to get around this,
* re retype to UW and use a stride.
*/
group_idx = retype(spread(group_idx, 2), BRW_REGISTER_TYPE_W);
group_idx = retype(spread(group_idx, 2), BRW_TYPE_W);
}
uint32_t src_start_offset = src.nr * REG_SIZE + src.subnr;
@ -706,7 +706,7 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
assert(inst->exec_size == 8 && inst->force_writemask_all);
assert(dst.file == BRW_GENERAL_REGISTER_FILE);
dst.type = BRW_REGISTER_TYPE_UD;
dst.type = BRW_TYPE_UD;
brw_inst *insn = brw_MOV(p, dst, brw_imm_ud(0));
if (devinfo->ver >= 12)
@ -717,7 +717,7 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
/* Copy the per-thread scratch space size from g0.3[3:0] */
brw_set_default_exec_size(p, BRW_EXECUTE_1);
insn = brw_AND(p, suboffset(dst, 3),
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 3), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(3, 0)));
if (devinfo->ver < 12) {
brw_inst_set_no_dd_clear(p->devinfo, insn, true);
@ -726,7 +726,7 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
/* Copy the scratch base address from g0.5[31:10] */
insn = brw_AND(p, suboffset(dst, 5),
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 5), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 10)));
if (devinfo->ver < 12)
brw_inst_set_no_dd_check(p->devinfo, insn, true);
@ -867,7 +867,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
* equality with a 32-bit value. See piglit fs-op-neg-uvec4.
*/
assert(!inst->conditional_mod ||
inst->src[i].type != BRW_REGISTER_TYPE_UD ||
inst->src[i].type != BRW_TYPE_UD ||
!inst->src[i].negate);
}
dst = brw_reg_from_fs_reg(devinfo, inst, &inst->dst);
@ -1017,22 +1017,22 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_CSEL(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_BFREV:
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
brw_BFREV(p, retype(dst, BRW_TYPE_UD),
retype(src[0], BRW_TYPE_UD));
break;
case BRW_OPCODE_FBH:
brw_FBH(p, retype(dst, src[0].type), src[0]);
break;
case BRW_OPCODE_FBL:
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
brw_FBL(p, retype(dst, BRW_TYPE_UD),
retype(src[0], BRW_TYPE_UD));
break;
case BRW_OPCODE_LZD:
brw_LZD(p, dst, src[0]);
break;
case BRW_OPCODE_CBIT:
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
brw_CBIT(p, retype(dst, BRW_TYPE_UD),
retype(src[0], BRW_TYPE_UD));
break;
case BRW_OPCODE_ADDC:
brw_ADDC(p, dst, src[0], src[1]);
@ -1119,8 +1119,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_PLN(p, dst, src[0], src[1]);
break;
case FS_OPCODE_PIXEL_X:
assert(src[0].type == BRW_REGISTER_TYPE_UW);
assert(src[1].type == BRW_REGISTER_TYPE_UW);
assert(src[0].type == BRW_TYPE_UW);
assert(src[1].type == BRW_TYPE_UW);
src[0].subnr = 0 * type_sz(src[0].type);
if (src[1].file == BRW_IMMEDIATE_VALUE) {
assert(src[1].ud == 0);
@ -1131,8 +1131,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
}
break;
case FS_OPCODE_PIXEL_Y:
assert(src[0].type == BRW_REGISTER_TYPE_UW);
assert(src[1].type == BRW_REGISTER_TYPE_UW);
assert(src[0].type == BRW_TYPE_UW);
assert(src[1].type == BRW_TYPE_UW);
src[0].subnr = 4 * type_sz(src[0].type);
if (src[1].file == BRW_IMMEDIATE_VALUE) {
assert(src[1].ud == 0);
@ -1212,8 +1212,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
/* Emit a MOV to force a stall until the instruction producing the
* registers finishes.
*/
brw_MOV(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW),
retype(src[i], BRW_REGISTER_TYPE_UW));
brw_MOV(p, retype(brw_null_reg(), BRW_TYPE_UW),
retype(src[i], BRW_TYPE_UW));
}
if (inst->sources > 1)
@ -1233,8 +1233,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
assert(inst->dst.file == BAD_FILE);
brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_MOV(p, retype(brw_flag_subreg(inst->flag_subreg),
BRW_REGISTER_TYPE_UD),
retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD));
BRW_TYPE_UD),
retype(brw_mask_reg(0), BRW_TYPE_UD));
break;
}
case SHADER_OPCODE_BROADCAST:
@ -1258,7 +1258,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
case SHADER_OPCODE_QUAD_SWIZZLE:
assert(src[1].file == BRW_IMMEDIATE_VALUE);
assert(src[1].type == BRW_REGISTER_TYPE_UD);
assert(src[1].type == BRW_TYPE_UD);
generate_quad_swizzle(inst, dst, src[0], src[1].ud);
break;
@ -1267,9 +1267,9 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
devinfo->has_64bit_float) || type_sz(src[0].type) <= 4);
assert(!src[0].negate && !src[0].abs);
assert(src[1].file == BRW_IMMEDIATE_VALUE);
assert(src[1].type == BRW_REGISTER_TYPE_UD);
assert(src[1].type == BRW_TYPE_UD);
assert(src[2].file == BRW_IMMEDIATE_VALUE);
assert(src[2].type == BRW_REGISTER_TYPE_UD);
assert(src[2].type == BRW_TYPE_UD);
const unsigned component = src[1].ud;
const unsigned cluster_size = src[2].ud;
assert(inst->src[0].file != ARF);

26
src/intel/compiler/brw_fs_lower.cpp
View file

@ -37,7 +37,7 @@ brw_fs_lower_constant_loads(fs_visitor &s)
const unsigned block_sz = 64; /* Fetch one cacheline at a time. */
const fs_builder ubld = ibld.exec_all().group(block_sz / 4, 0);
const fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_UD);
const fs_reg dst = ubld.vgrf(BRW_TYPE_UD);
const unsigned base = pull_index * 4;
fs_reg srcs[PULL_UNIFORM_CONSTANT_SRCS];
@ -105,8 +105,8 @@ brw_fs_lower_load_payload(fs_visitor &s)
2 : 1;
if (inst->src[i].file != BAD_FILE)
ubld.group(8 * n, 0).MOV(retype(dst, BRW_REGISTER_TYPE_UD),
retype(inst->src[i], BRW_REGISTER_TYPE_UD));
ubld.group(8 * n, 0).MOV(retype(dst, BRW_TYPE_UD),
retype(inst->src[i], BRW_TYPE_UD));
dst = byte_offset(dst, n * REG_SIZE);
i += n;
@ -167,8 +167,8 @@ brw_fs_lower_sub_sat(fs_visitor &s)
* same situations as #1 above. It is further limited by only
* allowing UD sources.
*/
if (inst->exec_size == 8 && inst->src[0].type != BRW_REGISTER_TYPE_Q &&
inst->src[0].type != BRW_REGISTER_TYPE_UQ) {
if (inst->exec_size == 8 && inst->src[0].type != BRW_TYPE_Q &&
inst->src[0].type != BRW_TYPE_UQ) {
fs_reg acc = retype(brw_acc_reg(inst->exec_size),
inst->src[1].type);
@ -387,7 +387,7 @@ brw_fs_lower_find_live_channel(fs_visitor &s)
* instruction has execution masking disabled, so it's kind of
* useless there.
*/
fs_reg exec_mask(retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD));
fs_reg exec_mask(retype(brw_mask_reg(0), BRW_TYPE_UD));
const fs_builder ibld(&s, block, inst);
if (!inst->is_partial_write())
@ -403,7 +403,7 @@ brw_fs_lower_find_live_channel(fs_visitor &s)
* will appear at the front of the mask.
*/
if (!(first && packed_dispatch)) {
fs_reg mask = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg mask = ubld.vgrf(BRW_TYPE_UD);
ubld.UNDEF(mask);
ubld.emit(SHADER_OPCODE_READ_SR_REG, mask, brw_imm_ud(vmask ? 3 : 2));
@ -424,7 +424,7 @@ brw_fs_lower_find_live_channel(fs_visitor &s)
break;
case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: {
fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg tmp = ubld.vgrf(BRW_TYPE_UD);
ubld.UNDEF(tmp);
ubld.LZD(tmp, exec_mask);
ubld.ADD(inst->dst, negate(tmp), brw_imm_uw(31));
@ -472,12 +472,12 @@ brw_fs_lower_sends_overlapping_payload(fs_visitor &s)
const unsigned len = MIN2(inst->mlen, inst->ex_mlen);
fs_reg tmp = fs_reg(VGRF, s.alloc.allocate(len),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
/* Sadly, we've lost all notion of channels and bit sizes at this
* point. Just WE_all it.
*/
const fs_builder ibld = fs_builder(&s, block, inst).exec_all().group(16, 0);
fs_reg copy_src = retype(inst->src[arg], BRW_REGISTER_TYPE_UD);
fs_reg copy_src = retype(inst->src[arg], BRW_TYPE_UD);
fs_reg copy_dst = tmp;
for (unsigned i = 0; i < len; i += 2) {
if (len == i + 1) {
@ -528,9 +528,9 @@ static bool
unsupported_64bit_type(const intel_device_info *devinfo,
enum brw_reg_type type)
{
return (!devinfo->has_64bit_float && type == BRW_REGISTER_TYPE_DF) ||
(!devinfo->has_64bit_int && (type == BRW_REGISTER_TYPE_UQ ||
type == BRW_REGISTER_TYPE_Q));
return (!devinfo->has_64bit_float && type == BRW_TYPE_DF) ||
(!devinfo->has_64bit_int && (type == BRW_TYPE_UQ ||
type == BRW_TYPE_Q));
}
/**

94
src/intel/compiler/brw_fs_lower_dpas.cpp
View file

@ -17,12 +17,12 @@ f16_using_mac(const fs_builder &bld, fs_inst *inst)
if (!inst->src[0].is_null())
assert(inst->dst.type == inst->src[0].type);
assert(inst->src[1].type == BRW_REGISTER_TYPE_HF);
assert(inst->src[2].type == BRW_REGISTER_TYPE_HF);
assert(inst->src[1].type == BRW_TYPE_HF);
assert(inst->src[2].type == BRW_TYPE_HF);
const brw_reg_type src0_type = inst->dst.type;
const brw_reg_type src1_type = BRW_REGISTER_TYPE_HF;
const brw_reg_type src2_type = BRW_REGISTER_TYPE_HF;
const brw_reg_type src1_type = BRW_TYPE_HF;
const brw_reg_type src2_type = BRW_TYPE_HF;
const fs_reg dest = inst->dst;
fs_reg src0 = inst->src[0];
@ -30,10 +30,10 @@ f16_using_mac(const fs_builder &bld, fs_inst *inst)
const fs_reg src2 = retype(inst->src[2], src2_type);
const unsigned dest_stride =
dest.type == BRW_REGISTER_TYPE_HF ? REG_SIZE / 2 : REG_SIZE;
dest.type == BRW_TYPE_HF ? REG_SIZE / 2 : REG_SIZE;
for (unsigned r = 0; r < inst->rcount; r++) {
fs_reg temp = bld.vgrf(BRW_REGISTER_TYPE_HF);
fs_reg temp = bld.vgrf(BRW_TYPE_HF);
for (unsigned subword = 0; subword < 2; subword++) {
for (unsigned s = 0; s < inst->sdepth; s++) {
@ -50,21 +50,21 @@ f16_using_mac(const fs_builder &bld, fs_inst *inst)
*/
if (s == 0 && subword == 0) {
const unsigned acc_width = 8;
fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_REGISTER_TYPE_UD),
fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_TYPE_UD),
inst->group % acc_width);
if (bld.shader->devinfo->verx10 >= 125) {
acc = subscript(acc, BRW_REGISTER_TYPE_HF, subword);
acc = subscript(acc, BRW_TYPE_HF, subword);
} else {
acc = retype(acc, BRW_REGISTER_TYPE_HF);
acc = retype(acc, BRW_TYPE_HF);
}
bld.MUL(acc,
subscript(retype(byte_offset(src1, s * REG_SIZE),
BRW_REGISTER_TYPE_UD),
BRW_REGISTER_TYPE_HF, subword),
BRW_TYPE_UD),
BRW_TYPE_HF, subword),
component(retype(byte_offset(src2, r * REG_SIZE),
BRW_REGISTER_TYPE_HF),
BRW_TYPE_HF),
s * 2 + subword))
->writes_accumulator = true;
@ -80,14 +80,14 @@ f16_using_mac(const fs_builder &bld, fs_inst *inst)
if ((s + 1) == inst->sdepth && subword == 1)
result = temp;
else
result = retype(bld.null_reg_ud(), BRW_REGISTER_TYPE_HF);
result = retype(bld.null_reg_ud(), BRW_TYPE_HF);
bld.MAC(result,
subscript(retype(byte_offset(src1, s * REG_SIZE),
BRW_REGISTER_TYPE_UD),
BRW_REGISTER_TYPE_HF, subword),
BRW_TYPE_UD),
BRW_TYPE_HF, subword),
component(retype(byte_offset(src2, r * REG_SIZE),
BRW_REGISTER_TYPE_HF),
BRW_TYPE_HF),
s * 2 + subword))
->writes_accumulator = true;
}
@ -95,7 +95,7 @@ f16_using_mac(const fs_builder &bld, fs_inst *inst)
}
if (!src0.is_null()) {
if (src0_type != BRW_REGISTER_TYPE_HF) {
if (src0_type != BRW_TYPE_HF) {
fs_reg temp2 = bld.vgrf(src0_type);
bld.MOV(temp2, temp);
@ -123,16 +123,16 @@ int8_using_dp4a(const fs_builder &bld, fs_inst *inst)
if (!inst->src[0].is_null())
assert(inst->dst.type == inst->src[0].type);
assert(inst->src[1].type == BRW_REGISTER_TYPE_B ||
inst->src[1].type == BRW_REGISTER_TYPE_UB);
assert(inst->src[2].type == BRW_REGISTER_TYPE_B ||
inst->src[2].type == BRW_REGISTER_TYPE_UB);
assert(inst->src[1].type == BRW_TYPE_B ||
inst->src[1].type == BRW_TYPE_UB);
assert(inst->src[2].type == BRW_TYPE_B ||
inst->src[2].type == BRW_TYPE_UB);
const brw_reg_type src1_type = inst->src[1].type == BRW_REGISTER_TYPE_UB
? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
const brw_reg_type src1_type = inst->src[1].type == BRW_TYPE_UB
? BRW_TYPE_UD : BRW_TYPE_D;
const brw_reg_type src2_type = inst->src[2].type == BRW_REGISTER_TYPE_UB
? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
const brw_reg_type src2_type = inst->src[2].type == BRW_TYPE_UB
? BRW_TYPE_UD : BRW_TYPE_D;
fs_reg dest = inst->dst;
fs_reg src0 = inst->src[0];
@ -170,18 +170,18 @@ int8_using_mul_add(const fs_builder &bld, fs_inst *inst)
if (!inst->src[0].is_null())
assert(inst->dst.type == inst->src[0].type);
assert(inst->src[1].type == BRW_REGISTER_TYPE_B ||
inst->src[1].type == BRW_REGISTER_TYPE_UB);
assert(inst->src[2].type == BRW_REGISTER_TYPE_B ||
inst->src[2].type == BRW_REGISTER_TYPE_UB);
assert(inst->src[1].type == BRW_TYPE_B ||
inst->src[1].type == BRW_TYPE_UB);
assert(inst->src[2].type == BRW_TYPE_B ||
inst->src[2].type == BRW_TYPE_UB);
const brw_reg_type src0_type = inst->dst.type;
const brw_reg_type src1_type = inst->src[1].type == BRW_REGISTER_TYPE_UB
? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
const brw_reg_type src1_type = inst->src[1].type == BRW_TYPE_UB
? BRW_TYPE_UD : BRW_TYPE_D;
const brw_reg_type src2_type = inst->src[2].type == BRW_REGISTER_TYPE_UB
? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
const brw_reg_type src2_type = inst->src[2].type == BRW_TYPE_UB
? BRW_TYPE_UD : BRW_TYPE_D;
fs_reg dest = inst->dst;
fs_reg src0 = inst->src[0];
@ -199,13 +199,13 @@ int8_using_mul_add(const fs_builder &bld, fs_inst *inst)
}
for (unsigned s = 0; s < inst->sdepth; s++) {
fs_reg temp1 = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg temp2 = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg temp3 = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
fs_reg temp1 = bld.vgrf(BRW_TYPE_UD);
fs_reg temp2 = bld.vgrf(BRW_TYPE_UD);
fs_reg temp3 = bld.vgrf(BRW_TYPE_UD, 2);
const brw_reg_type temp_type =
(inst->src[1].type == BRW_REGISTER_TYPE_B ||
inst->src[2].type == BRW_REGISTER_TYPE_B)
? BRW_REGISTER_TYPE_W : BRW_REGISTER_TYPE_UW;
(inst->src[1].type == BRW_TYPE_B ||
inst->src[2].type == BRW_TYPE_B)
? BRW_TYPE_W : BRW_TYPE_UW;
/* Expand 8 dwords of packed bytes into 16 dwords of packed
* words.
@ -220,37 +220,37 @@ int8_using_mul_add(const fs_builder &bld, fs_inst *inst)
bld.MUL(subscript(temp1, temp_type, 0),
subscript(retype(byte_offset(src1, s * REG_SIZE),
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
inst->src[1].type, 0),
subscript(component(retype(temp3,
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
s * 2),
temp_type, 0));
bld.MUL(subscript(temp1, temp_type, 1),
subscript(retype(byte_offset(src1, s * REG_SIZE),
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
inst->src[1].type, 1),
subscript(component(retype(temp3,
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
s * 2),
temp_type, 1));
bld.MUL(subscript(temp2, temp_type, 0),
subscript(retype(byte_offset(src1, s * REG_SIZE),
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
inst->src[1].type, 2),
subscript(component(retype(temp3,
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
s * 2 + 1),
temp_type, 0));
bld.MUL(subscript(temp2, temp_type, 1),
subscript(retype(byte_offset(src1, s * REG_SIZE),
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
inst->src[1].type, 3),
subscript(component(retype(temp3,
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
s * 2 + 1),
temp_type, 1));

80
src/intel/compiler/brw_fs_lower_integer_multiplication.cpp
View file

@ -283,16 +283,16 @@ brw_fs_lower_mul_dword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block)
}
} else {
ibld.MUL(low, inst->src[0],
subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 0));
subscript(inst->src[1], BRW_TYPE_UW, 0));
ibld.MUL(high, inst->src[0],
subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 1));
subscript(inst->src[1], BRW_TYPE_UW, 1));
}
}
if (do_addition) {
ibld.ADD(subscript(low, BRW_REGISTER_TYPE_UW, 1),
subscript(low, BRW_REGISTER_TYPE_UW, 1),
subscript(high, BRW_REGISTER_TYPE_UW, 0));
ibld.ADD(subscript(low, BRW_TYPE_UW, 1),
subscript(low, BRW_TYPE_UW, 1),
subscript(high, BRW_TYPE_UW, 0));
}
if (needs_mov || inst->conditional_mod)
@ -319,53 +319,53 @@ brw_fs_lower_mul_qword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block)
unsigned int q_regs = regs_written(inst);
unsigned int d_regs = (q_regs + 1) / 2;
fs_reg bd(VGRF, s.alloc.allocate(q_regs), BRW_REGISTER_TYPE_UQ);
fs_reg ad(VGRF, s.alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
fs_reg bc(VGRF, s.alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
fs_reg bd(VGRF, s.alloc.allocate(q_regs), BRW_TYPE_UQ);
fs_reg ad(VGRF, s.alloc.allocate(d_regs), BRW_TYPE_UD);
fs_reg bc(VGRF, s.alloc.allocate(d_regs), BRW_TYPE_UD);
/* Here we need the full 64 bit result for 32b * 32b. */
if (devinfo->has_integer_dword_mul) {
ibld.MUL(bd, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0));
ibld.MUL(bd, subscript(inst->src[0], BRW_TYPE_UD, 0),
subscript(inst->src[1], BRW_TYPE_UD, 0));
} else {
fs_reg bd_high(VGRF, s.alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
fs_reg bd_low(VGRF, s.alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
fs_reg bd_high(VGRF, s.alloc.allocate(d_regs), BRW_TYPE_UD);
fs_reg bd_low(VGRF, s.alloc.allocate(d_regs), BRW_TYPE_UD);
const unsigned acc_width = reg_unit(devinfo) * 8;
fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_REGISTER_TYPE_UD),
fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_TYPE_UD),
inst->group % acc_width);
fs_inst *mul = ibld.MUL(acc,
subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 0));
subscript(inst->src[0], BRW_TYPE_UD, 0),
subscript(inst->src[1], BRW_TYPE_UW, 0));
mul->writes_accumulator = true;
ibld.MACH(bd_high, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0));
ibld.MACH(bd_high, subscript(inst->src[0], BRW_TYPE_UD, 0),
subscript(inst->src[1], BRW_TYPE_UD, 0));
ibld.MOV(bd_low, acc);
ibld.UNDEF(bd);
ibld.MOV(subscript(bd, BRW_REGISTER_TYPE_UD, 0), bd_low);
ibld.MOV(subscript(bd, BRW_REGISTER_TYPE_UD, 1), bd_high);
ibld.MOV(subscript(bd, BRW_TYPE_UD, 0), bd_low);
ibld.MOV(subscript(bd, BRW_TYPE_UD, 1), bd_high);
}
ibld.MUL(ad, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1),
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0));
ibld.MUL(bc, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 1));
ibld.MUL(ad, subscript(inst->src[0], BRW_TYPE_UD, 1),
subscript(inst->src[1], BRW_TYPE_UD, 0));
ibld.MUL(bc, subscript(inst->src[0], BRW_TYPE_UD, 0),
subscript(inst->src[1], BRW_TYPE_UD, 1));
ibld.ADD(ad, ad, bc);
ibld.ADD(subscript(bd, BRW_REGISTER_TYPE_UD, 1),
subscript(bd, BRW_REGISTER_TYPE_UD, 1), ad);
ibld.ADD(subscript(bd, BRW_TYPE_UD, 1),
subscript(bd, BRW_TYPE_UD, 1), ad);
if (devinfo->has_64bit_int) {
ibld.MOV(inst->dst, bd);
} else {
if (!inst->is_partial_write())
ibld.emit_undef_for_dst(inst);
ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0),
subscript(bd, BRW_REGISTER_TYPE_UD, 0));
ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1),
subscript(bd, BRW_REGISTER_TYPE_UD, 1));
ibld.MOV(subscript(inst->dst, BRW_TYPE_UD, 0),
subscript(bd, BRW_TYPE_UD, 0));
ibld.MOV(subscript(inst->dst, BRW_TYPE_UD, 1),
subscript(bd, BRW_TYPE_UD, 1));
}
}
@ -403,9 +403,9 @@ brw_fs_lower_mulh_inst(fs_visitor &s, fs_inst *inst, bblock_t *block)
* multiply, but in order to do a 64-bit multiply we can simulate
* the previous behavior and then use a MACH instruction.
*/
assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
mul->src[1].type == BRW_REGISTER_TYPE_UD);
mul->src[1].type = BRW_REGISTER_TYPE_UW;
assert(mul->src[1].type == BRW_TYPE_D ||
mul->src[1].type == BRW_TYPE_UD);
mul->src[1].type = BRW_TYPE_UW;
mul->src[1].stride *= 2;
if (mul->src[1].file == IMM) {
@ -427,18 +427,18 @@ brw_fs_lower_integer_multiplication(fs_visitor &s)
if (type_sz(inst->src[1].type) < 4 && type_sz(inst->src[0].type) <= 4)
continue;
if ((inst->dst.type == BRW_REGISTER_TYPE_Q ||
inst->dst.type == BRW_REGISTER_TYPE_UQ) &&
(inst->src[0].type == BRW_REGISTER_TYPE_Q ||
inst->src[0].type == BRW_REGISTER_TYPE_UQ) &&
(inst->src[1].type == BRW_REGISTER_TYPE_Q ||
inst->src[1].type == BRW_REGISTER_TYPE_UQ)) {
if ((inst->dst.type == BRW_TYPE_Q ||
inst->dst.type == BRW_TYPE_UQ) &&
(inst->src[0].type == BRW_TYPE_Q ||
inst->src[0].type == BRW_TYPE_UQ) &&
(inst->src[1].type == BRW_TYPE_Q ||
inst->src[1].type == BRW_TYPE_UQ)) {
brw_fs_lower_mul_qword_inst(s, inst, block);
inst->remove(block);
progress = true;
} else if (!inst->dst.is_accumulator() &&
(inst->dst.type == BRW_REGISTER_TYPE_D ||
inst->dst.type == BRW_REGISTER_TYPE_UD) &&
(inst->dst.type == BRW_TYPE_D ||
inst->dst.type == BRW_TYPE_UD) &&
(!devinfo->has_integer_dword_mul ||
devinfo->verx10 >= 125)) {
brw_fs_lower_mul_dword_inst(s, inst, block);

6
src/intel/compiler/brw_fs_lower_pack.cpp
View file

@ -57,15 +57,15 @@ brw_fs_lower_pack(fs_visitor &s)
ibld.MOV(subscript(dst, inst->src[i].type, i), inst->src[i]);
break;
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
assert(dst.type == BRW_REGISTER_TYPE_UD);
assert(dst.type == BRW_TYPE_UD);
for (unsigned i = 0; i < inst->sources; i++) {
if (inst->src[i].file == IMM) {
const uint32_t half = _mesa_float_to_half(inst->src[i].f);
ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_UW, i),
ibld.MOV(subscript(dst, BRW_TYPE_UW, i),
brw_imm_uw(half));
} else {
ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_HF, i),
ibld.MOV(subscript(dst, BRW_TYPE_HF, i),
inst->src[i]);
}
}

8
src/intel/compiler/brw_fs_lower_regioning.cpp
View file

@ -240,7 +240,7 @@ namespace {
*/
if ((!devinfo->has_64bit_int ||
intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4)
return BRW_REGISTER_TYPE_UD;
return BRW_TYPE_UD;
else if (has_dst_aligned_region_restriction(devinfo, inst))
return brw_int_type(type_sz(t), false);
else
@ -249,7 +249,7 @@ namespace {
case SHADER_OPCODE_SEL_EXEC:
if ((!has_64bit || devinfo->has_64bit_float_via_math_pipe) &&
type_sz(t) > 4)
return BRW_REGISTER_TYPE_UD;
return BRW_TYPE_UD;
else
return t;
@ -277,7 +277,7 @@ namespace {
*/
if ((!has_64bit || devinfo->verx10 >= 125 ||
intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4)
return BRW_REGISTER_TYPE_UD;
return BRW_TYPE_UD;
else
return brw_int_type(type_sz(t), false);
@ -301,7 +301,7 @@ namespace {
* a vector before using in a HF (packed or unpacked) math operation.
*/
if (inst->is_math() && intel_needs_workaround(devinfo, 22016140776) &&
is_uniform(inst->src[i]) && inst->src[i].type == BRW_REGISTER_TYPE_HF) {
is_uniform(inst->src[i]) && inst->src[i].type == BRW_TYPE_HF) {
return true;
}

16
src/intel/compiler/brw_fs_lower_simd_width.cpp
View file

@ -11,11 +11,11 @@ using namespace brw;
static bool
is_mixed_float_with_fp32_dst(const fs_inst *inst)
{
if (inst->dst.type != BRW_REGISTER_TYPE_F)
if (inst->dst.type != BRW_TYPE_F)
return false;
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].type == BRW_REGISTER_TYPE_HF)
if (inst->src[i].type == BRW_TYPE_HF)
return true;
}
@ -25,12 +25,12 @@ is_mixed_float_with_fp32_dst(const fs_inst *inst)
static bool
is_mixed_float_with_packed_fp16_dst(const fs_inst *inst)
{
if (inst->dst.type != BRW_REGISTER_TYPE_HF ||
if (inst->dst.type != BRW_TYPE_HF ||
inst->dst.stride != 1)
return false;
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].type == BRW_REGISTER_TYPE_F)
if (inst->src[i].type == BRW_TYPE_F)
return true;
}
@ -203,11 +203,11 @@ get_sampler_lowered_simd_width(const struct intel_device_info *devinfo,
static bool
is_half_float_src_dst(const fs_inst *inst)
{
if (inst->dst.type == BRW_REGISTER_TYPE_HF)
if (inst->dst.type == BRW_TYPE_HF)
return true;
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].type == BRW_REGISTER_TYPE_HF)
if (inst->src[i].type == BRW_TYPE_HF)
return true;
}
@ -609,12 +609,12 @@ emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after,
const fs_builder rbld = lbld_after.exec_all().group(1, 0);
fs_reg local_res_reg = component(
retype(offset(tmp, lbld_before, dst_size),
BRW_REGISTER_TYPE_UW), 0);
BRW_TYPE_UW), 0);
fs_reg final_res_reg =
retype(byte_offset(inst->dst,
inst->size_written - residency_size +
lbld_after.group() / 8),
BRW_REGISTER_TYPE_UW);
BRW_TYPE_UW);
rbld.MOV(final_res_reg, local_res_reg);
}

750
src/intel/compiler/brw_fs_nir.cpp
View file

File diff suppressed because it is too large Load diff

40
src/intel/compiler/brw_fs_opt_algebraic.cpp
View file

@ -14,22 +14,22 @@ src_as_uint(const fs_reg &src)
assert(src.file == IMM);
switch (src.type) {
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_W:
return (uint64_t)(int16_t)(src.ud & 0xffff);
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_UW:
return (uint64_t)(uint16_t)(src.ud & 0xffff);
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
return (uint64_t)src.d;
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_UD:
return (uint64_t)src.ud;
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_Q:
return src.d64;
case BRW_REGISTER_TYPE_UQ:
case BRW_TYPE_UQ:
return src.u64;
default:
@ -41,22 +41,22 @@ static fs_reg
brw_imm_for_type(uint64_t value, enum brw_reg_type type)
{
switch (type) {
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_W:
return brw_imm_w(value);
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_UW:
return brw_imm_uw(value);
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
return brw_imm_d(value);
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_UD:
return brw_imm_ud(value);
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_Q:
return brw_imm_d(value);
case BRW_REGISTER_TYPE_UQ:
case BRW_TYPE_UQ:
return brw_imm_uq(value);
default:
@ -95,8 +95,8 @@ brw_fs_opt_algebraic(fs_visitor &s)
* Other mixed-size-but-same-base-type cases may also be possible.
*/
if (inst->dst.type != inst->src[0].type &&
inst->dst.type != BRW_REGISTER_TYPE_DF &&
inst->src[0].type != BRW_REGISTER_TYPE_F)
inst->dst.type != BRW_TYPE_DF &&
inst->src[0].type != BRW_TYPE_F)
assert(!"unimplemented: saturate mixed types");
if (fs_reg_saturate_immediate(&inst->src[0])) {
@ -189,7 +189,7 @@ brw_fs_opt_algebraic(fs_visitor &s)
}
if (inst->src[0].file == IMM) {
assert(inst->src[0].type == BRW_REGISTER_TYPE_F);
assert(inst->src[0].type == BRW_TYPE_F);
inst->opcode = BRW_OPCODE_MOV;
inst->sources = 1;
inst->src[0].f += inst->src[1].f;
@ -270,7 +270,7 @@ brw_fs_opt_algebraic(fs_visitor &s)
case BRW_CONDITIONAL_LE:
case BRW_CONDITIONAL_L:
switch (inst->src[1].type) {
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
if (inst->src[1].f >= 1.0f) {
inst->opcode = BRW_OPCODE_MOV;
inst->sources = 1;
@ -286,7 +286,7 @@ brw_fs_opt_algebraic(fs_visitor &s)
case BRW_CONDITIONAL_GE:
case BRW_CONDITIONAL_G:
switch (inst->src[1].type) {
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
if (inst->src[1].f <= 0.0f) {
inst->opcode = BRW_OPCODE_MOV;
inst->sources = 1;
@ -304,9 +304,9 @@ brw_fs_opt_algebraic(fs_visitor &s)
}
break;
case BRW_OPCODE_MAD:
if (inst->src[0].type != BRW_REGISTER_TYPE_F ||
inst->src[1].type != BRW_REGISTER_TYPE_F ||
inst->src[2].type != BRW_REGISTER_TYPE_F)
if (inst->src[0].type != BRW_TYPE_F ||
inst->src[1].type != BRW_TYPE_F ||
inst->src[2].type != BRW_TYPE_F)
break;
if (inst->src[1].is_one()) {
inst->opcode = BRW_OPCODE_ADD;

10
src/intel/compiler/brw_fs_reg_allocate.cpp
View file

@ -586,7 +586,7 @@ fs_reg_alloc::discard_interference_graph()
fs_reg
fs_reg_alloc::build_single_offset(const fs_builder &bld, uint32_t spill_offset, int ip)
{
fs_reg offset = retype(alloc_spill_reg(1, ip), BRW_REGISTER_TYPE_UD);
fs_reg offset = retype(alloc_spill_reg(1, ip), BRW_TYPE_UD);
fs_inst *inst = bld.MOV(offset, brw_imm_ud(spill_offset));
_mesa_set_add(spill_insts, inst);
return offset;
@ -601,14 +601,14 @@ fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, i
const fs_builder ubld = bld.exec_all();
const unsigned reg_count = ubld.dispatch_width() / 8;
fs_reg offset = retype(alloc_spill_reg(reg_count, ip), BRW_REGISTER_TYPE_UD);
fs_reg offset = retype(alloc_spill_reg(reg_count, ip), BRW_TYPE_UD);
fs_inst *inst;
/* Build an offset per lane in SIMD8 */
inst = ubld.group(8, 0).MOV(retype(offset, BRW_REGISTER_TYPE_UW),
inst = ubld.group(8, 0).MOV(retype(offset, BRW_TYPE_UW),
brw_imm_uv(0x76543210));
_mesa_set_add(spill_insts, inst);
inst = ubld.group(8, 0).MOV(offset, retype(offset, BRW_REGISTER_TYPE_UW));
inst = ubld.group(8, 0).MOV(offset, retype(offset, BRW_TYPE_UW));
_mesa_set_add(spill_insts, inst);
/* Build offsets in the upper 8 lanes of SIMD16 */
@ -910,7 +910,7 @@ fs_reg_alloc::alloc_scratch_header()
setup_live_interference(scratch_header_node, 0, INT_MAX);
return fs_reg(VGRF, vgrf, BRW_REGISTER_TYPE_UD);
return fs_reg(VGRF, vgrf, BRW_TYPE_UD);
}
fs_reg

4
src/intel/compiler/brw_fs_scoreboard.cpp
View file

@ -1019,8 +1019,8 @@ namespace {
const bool is_unordered_math =
(inst->is_math() && devinfo->ver < 20) ||
(devinfo->has_64bit_float_via_math_pipe &&
(get_exec_type(inst) == BRW_REGISTER_TYPE_DF ||
inst->dst.type == BRW_REGISTER_TYPE_DF));
(get_exec_type(inst) == BRW_TYPE_DF ||
inst->dst.type == BRW_TYPE_DF));
/* Track any source registers that may be fetched asynchronously by this
* instruction, otherwise clear the dependency in order to avoid

16
src/intel/compiler/brw_fs_thread_payload.cpp
View file

@ -83,7 +83,7 @@ tes_thread_payload::tes_thread_payload(const fs_visitor &v)
unsigned r = 0;
/* R0: Thread Header. */
patch_urb_input = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD);
patch_urb_input = retype(brw_vec1_grf(0, 0), BRW_TYPE_UD);
primitive_id = brw_vec1_grf(0, 1);
r += reg_unit(v.devinfo);
@ -110,12 +110,12 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v)
unsigned r = reg_unit(v.devinfo);
/* R1: output URB handles. */
urb_handles = bld.vgrf(BRW_REGISTER_TYPE_UD);
urb_handles = bld.vgrf(BRW_TYPE_UD);
bld.AND(urb_handles, brw_ud8_grf(r, 0),
v.devinfo->ver >= 20 ? brw_imm_ud(0xFFFFFF) : brw_imm_ud(0xFFFF));
/* R1: Instance ID stored in bits 31:27 */
instance_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
instance_id = bld.vgrf(BRW_TYPE_UD);
bld.SHR(instance_id, brw_ud8_grf(r, 0), brw_imm_ud(27u));
r += reg_unit(v.devinfo);
@ -389,7 +389,7 @@ cs_thread_payload::load_subgroup_id(const fs_builder &bld,
fs_reg &dest) const
{
auto devinfo = bld.shader->devinfo;
dest = retype(dest, BRW_REGISTER_TYPE_UD);
dest = retype(dest, BRW_TYPE_UD);
if (subgroup_id_.file != BAD_FILE) {
assert(devinfo->verx10 >= 125);
@ -399,7 +399,7 @@ cs_thread_payload::load_subgroup_id(const fs_builder &bld,
assert(gl_shader_stage_is_compute(bld.shader->stage));
int index = brw_get_subgroup_id_param_index(devinfo,
bld.shader->prog_data);
bld.MOV(dest, fs_reg(UNIFORM, index, BRW_REGISTER_TYPE_UD));
bld.MOV(dest, fs_reg(UNIFORM, index, BRW_TYPE_UD));
}
}
@ -429,12 +429,12 @@ task_mesh_thread_payload::task_mesh_thread_payload(fs_visitor &v)
unsigned r = 0;
assert(subgroup_id_.file != BAD_FILE);
extended_parameter_0 = retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD);
extended_parameter_0 = retype(brw_vec1_grf(0, 3), BRW_TYPE_UD);
if (v.devinfo->ver >= 20) {
urb_output = brw_ud1_grf(1, 0);
} else {
urb_output = bld.vgrf(BRW_REGISTER_TYPE_UD);
urb_output = bld.vgrf(BRW_TYPE_UD);
/* In both mesh and task shader payload, lower 16 bits of g0.6 is
* an offset within Slice's Local URB, which says where shader is
* supposed to output its data.
@ -485,7 +485,7 @@ bs_thread_payload::bs_thread_payload(const fs_visitor &v)
void
bs_thread_payload::load_shader_type(const fs_builder &bld, fs_reg &dest) const
{
fs_reg ud_dest = retype(dest, BRW_REGISTER_TYPE_UD);
fs_reg ud_dest = retype(dest, BRW_TYPE_UD);
bld.MOV(ud_dest, retype(brw_vec1_grf(0, 3), ud_dest.type));
bld.AND(ud_dest, ud_dest, brw_imm_ud(0xf));
}

2
src/intel/compiler/brw_fs_validate.cpp
View file

@ -211,7 +211,7 @@ brw_fs_validate(const fs_visitor &s)
*/
for (unsigned i = 0; i < inst->sources; i++) {
fsv_assert(!is_uniform(inst->src[i]) ||
inst->src[i].type != BRW_REGISTER_TYPE_HF);
inst->src[i].type != BRW_TYPE_HF);
}
}
}

106
src/intel/compiler/brw_fs_visitor.cpp
View file

@ -70,12 +70,12 @@ fs_visitor::interp_reg(const fs_builder &bld, unsigned location,
* assign_urb_setup()), so we need to use offset() instead of
* component() to select the specified parameter.
*/
const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.MOV(tmp, offset(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_UD),
const fs_reg tmp = bld.vgrf(BRW_TYPE_UD);
bld.MOV(tmp, offset(fs_reg(ATTR, regnr, BRW_TYPE_UD),
dispatch_width, comp));
return retype(tmp, BRW_REGISTER_TYPE_F);
return retype(tmp, BRW_TYPE_F);
} else {
return component(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F), comp);
return component(fs_reg(ATTR, regnr, BRW_TYPE_F), comp);
}
}
@ -105,12 +105,12 @@ fs_visitor::per_primitive_reg(const fs_builder &bld, int location, unsigned comp
* assign_urb_setup()), so we need to use offset() instead of
* component() to select the specified parameter.
*/
const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.MOV(tmp, offset(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_UD),
const fs_reg tmp = bld.vgrf(BRW_TYPE_UD);
bld.MOV(tmp, offset(fs_reg(ATTR, regnr, BRW_TYPE_UD),
dispatch_width, comp % 4));
return retype(tmp, BRW_REGISTER_TYPE_F);
return retype(tmp, BRW_TYPE_F);
} else {
return component(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F), comp % 4);
return component(fs_reg(ATTR, regnr, BRW_TYPE_F), comp % 4);
}
}
@ -121,8 +121,8 @@ fs_visitor::emit_interpolation_setup()
const fs_builder bld = fs_builder(this).at_end();
fs_builder abld = bld.annotate("compute pixel centers");
this->pixel_x = bld.vgrf(BRW_REGISTER_TYPE_F);
this->pixel_y = bld.vgrf(BRW_REGISTER_TYPE_F);
this->pixel_x = bld.vgrf(BRW_TYPE_F);
this->pixel_y = bld.vgrf(BRW_TYPE_F);
const struct brw_wm_prog_key *wm_key = (brw_wm_prog_key*) this->key;
struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data);
@ -186,7 +186,7 @@ fs_visitor::emit_interpolation_setup()
*
* The coarse pixel size is delivered as 2 u8 in r1.0
*/
struct brw_reg r1_0 = retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), BRW_REGISTER_TYPE_UB);
struct brw_reg r1_0 = retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), BRW_TYPE_UB);
const fs_builder dbld =
abld.exec_all().group(MIN2(16, dispatch_width) * 2, 0);
@ -195,31 +195,31 @@ fs_visitor::emit_interpolation_setup()
/* To build the array of half bytes we do and AND operation with the
* right mask in X.
*/
int_coarse_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
int_coarse_offset_x = dbld.vgrf(BRW_TYPE_UW);
dbld.AND(int_coarse_offset_x, byte_offset(r1_0, 0), brw_imm_v(0x0f000f00));
/* And the right mask in Y. */
int_coarse_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
int_coarse_offset_y = dbld.vgrf(BRW_TYPE_UW);
dbld.AND(int_coarse_offset_y, byte_offset(r1_0, 1), brw_imm_v(0x0f0f0000));
} else {
/* To build the array of half bytes we do and AND operation with the
* right mask in X.
*/
int_coarse_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
int_coarse_offset_x = dbld.vgrf(BRW_TYPE_UW);
dbld.AND(int_coarse_offset_x, byte_offset(r1_0, 0), brw_imm_v(0x0000f0f0));
/* And the right mask in Y. */
int_coarse_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
int_coarse_offset_y = dbld.vgrf(BRW_TYPE_UW);
dbld.AND(int_coarse_offset_y, byte_offset(r1_0, 1), brw_imm_v(0xff000000));
/* Finally OR the 2 registers. */
int_coarse_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
int_coarse_offset_xy = dbld.vgrf(BRW_TYPE_UW);
dbld.OR(int_coarse_offset_xy, int_coarse_offset_x, int_coarse_offset_y);
}
/* Also compute the half coarse size used to center coarses. */
half_int_coarse_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW);
half_int_coarse_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW);
half_int_coarse_offset_x = bld.vgrf(BRW_TYPE_UW);
half_int_coarse_offset_y = bld.vgrf(BRW_TYPE_UW);
bld.SHR(half_int_coarse_offset_x, suboffset(r1_0, 0), brw_imm_ud(1));
bld.SHR(half_int_coarse_offset_y, suboffset(r1_0, 1), brw_imm_ud(1));
@ -244,31 +244,31 @@ fs_visitor::emit_interpolation_setup()
check_dynamic_msaa_flag(dbld, wm_prog_data,
INTEL_MSAA_FLAG_COARSE_RT_WRITES);
int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
int_pixel_offset_x = dbld.vgrf(BRW_TYPE_UW);
set_predicate(BRW_PREDICATE_NORMAL,
dbld.SEL(int_pixel_offset_x,
int_coarse_offset_x,
int_sample_offset_x));
int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
int_pixel_offset_y = dbld.vgrf(BRW_TYPE_UW);
set_predicate(BRW_PREDICATE_NORMAL,
dbld.SEL(int_pixel_offset_y,
int_coarse_offset_y,
int_sample_offset_y));
int_pixel_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
int_pixel_offset_xy = dbld.vgrf(BRW_TYPE_UW);
set_predicate(BRW_PREDICATE_NORMAL,
dbld.SEL(int_pixel_offset_xy,
int_coarse_offset_xy,
int_sample_offset_xy));
half_int_pixel_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW);
half_int_pixel_offset_x = bld.vgrf(BRW_TYPE_UW);
set_predicate(BRW_PREDICATE_NORMAL,
bld.SEL(half_int_pixel_offset_x,
half_int_coarse_offset_x,
half_int_sample_offset_x));
half_int_pixel_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW);
half_int_pixel_offset_y = bld.vgrf(BRW_TYPE_UW);
set_predicate(BRW_PREDICATE_NORMAL,
bld.SEL(half_int_pixel_offset_y,
half_int_coarse_offset_y,
@ -295,13 +295,13 @@ fs_visitor::emit_interpolation_setup()
*/
const struct brw_reg gi_reg = devinfo->ver >= 20 ? xe2_vec1_grf(i, 8) :
brw_vec1_grf(i + 1, 0);
const struct brw_reg gi_uw = retype(gi_reg, BRW_REGISTER_TYPE_UW);
const struct brw_reg gi_uw = retype(gi_reg, BRW_TYPE_UW);
if (devinfo->verx10 >= 125) {
const fs_builder dbld =
abld.exec_all().group(hbld.dispatch_width() * 2, 0);
const fs_reg int_pixel_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
const fs_reg int_pixel_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
const fs_reg int_pixel_x = dbld.vgrf(BRW_TYPE_UW);
const fs_reg int_pixel_y = dbld.vgrf(BRW_TYPE_UW);
dbld.ADD(int_pixel_x,
fs_reg(stride(suboffset(gi_uw, 4), 2, 8, 0)),
@ -337,7 +337,7 @@ fs_visitor::emit_interpolation_setup()
*/
const fs_builder dbld =
abld.exec_all().group(hbld.dispatch_width() * 2, 0);
fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
fs_reg int_pixel_xy = dbld.vgrf(BRW_TYPE_UW);
dbld.ADD(int_pixel_xy,
fs_reg(stride(suboffset(gi_uw, 4), 1, 4, 0)),
@ -365,23 +365,23 @@ fs_visitor::emit_interpolation_setup()
const fs_reg z_cy = brw_vec1_grf(coef_payload.nr, 0);
const fs_reg z_c0 = brw_vec1_grf(coef_payload.nr, 3);
const fs_reg float_pixel_x = abld.vgrf(BRW_REGISTER_TYPE_F);
const fs_reg float_pixel_y = abld.vgrf(BRW_REGISTER_TYPE_F);
const fs_reg float_pixel_x = abld.vgrf(BRW_TYPE_F);
const fs_reg float_pixel_y = abld.vgrf(BRW_TYPE_F);
abld.ADD(float_pixel_x, this->pixel_x, negate(x_start));
abld.ADD(float_pixel_y, this->pixel_y, negate(y_start));
/* r1.0 - 0:7 ActualCoarsePixelShadingSize.X */
const fs_reg u8_cps_width = fs_reg(retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UB));
const fs_reg u8_cps_width = fs_reg(retype(brw_vec1_grf(1, 0), BRW_TYPE_UB));
/* r1.0 - 15:8 ActualCoarsePixelShadingSize.Y */
const fs_reg u8_cps_height = byte_offset(u8_cps_width, 1);
const fs_reg u32_cps_width = abld.vgrf(BRW_REGISTER_TYPE_UD);
const fs_reg u32_cps_height = abld.vgrf(BRW_REGISTER_TYPE_UD);
const fs_reg u32_cps_width = abld.vgrf(BRW_TYPE_UD);
const fs_reg u32_cps_height = abld.vgrf(BRW_TYPE_UD);
abld.MOV(u32_cps_width, u8_cps_width);
abld.MOV(u32_cps_height, u8_cps_height);
const fs_reg f_cps_width = abld.vgrf(BRW_REGISTER_TYPE_F);
const fs_reg f_cps_height = abld.vgrf(BRW_REGISTER_TYPE_F);
const fs_reg f_cps_width = abld.vgrf(BRW_TYPE_F);
const fs_reg f_cps_height = abld.vgrf(BRW_TYPE_F);
abld.MOV(f_cps_width, u32_cps_width);
abld.MOV(f_cps_height, u32_cps_height);
@ -389,7 +389,7 @@ fs_visitor::emit_interpolation_setup()
abld.MAD(float_pixel_x, float_pixel_x, brw_imm_f(0.5f), f_cps_width);
abld.MAD(float_pixel_y, float_pixel_y, brw_imm_f(0.5f), f_cps_height);
coarse_z = abld.vgrf(BRW_REGISTER_TYPE_F);
coarse_z = abld.vgrf(BRW_TYPE_F);
abld.MAD(coarse_z, z_c0, z_cx, float_pixel_x);
abld.MAD(coarse_z, coarse_z, z_cy, float_pixel_y);
}
@ -411,7 +411,7 @@ fs_visitor::emit_interpolation_setup()
case BRW_SOMETIMES:
assert(wm_prog_data->uses_src_depth);
assert(wm_prog_data->uses_depth_w_coefficients);
this->pixel_z = abld.vgrf(BRW_REGISTER_TYPE_F);
this->pixel_z = abld.vgrf(BRW_TYPE_F);
/* We re-use the check_dynamic_msaa_flag() call from above */
set_predicate(BRW_PREDICATE_NORMAL,
@ -429,7 +429,7 @@ fs_visitor::emit_interpolation_setup()
if (wm_prog_data->uses_src_w) {
abld = bld.annotate("compute pos.w");
this->pixel_w = fetch_payload_reg(abld, fs_payload().source_w_reg);
this->wpos_w = bld.vgrf(BRW_REGISTER_TYPE_F);
this->wpos_w = bld.vgrf(BRW_TYPE_F);
abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
}
@ -498,8 +498,8 @@ fs_visitor::emit_interpolation_setup()
*/
for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
bld.exec_all().group(1, 0)
.MOV(retype(brw_flag_reg(0, i), BRW_REGISTER_TYPE_UW),
retype(brw_vec1_grf(1 + i, 7), BRW_REGISTER_TYPE_UW));
.MOV(retype(brw_flag_reg(0, i), BRW_TYPE_UW),
retype(brw_vec1_grf(1 + i, 7), BRW_TYPE_UW));
}
for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
@ -509,7 +509,7 @@ fs_visitor::emit_interpolation_setup()
const fs_reg centroid_delta_xy = delta_xy[i];
const fs_reg &pixel_delta_xy = delta_xy[i - 1];
delta_xy[i] = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
delta_xy[i] = bld.vgrf(BRW_TYPE_F, 2);
for (unsigned c = 0; c < 2; c++) {
for (unsigned q = 0; q < dispatch_width / 8; q++) {
@ -592,7 +592,7 @@ fs_visitor::do_emit_fb_writes(int nr_color_regions, bool replicate_alpha)
*/
const fs_reg srcs[] = { reg_undef, reg_undef,
reg_undef, offset(this->outputs[0], bld, 3) };
const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 4);
const fs_reg tmp = bld.vgrf(BRW_TYPE_UD, 4);
bld.LOAD_PAYLOAD(tmp, srcs, 4, 0);
inst = emit_single_fb_write(bld, tmp, reg_undef, reg_undef, 4);
@ -725,7 +725,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
per_slot_offsets = brw_imm_ud(output_vertex_size *
gs_vertex_count.ud);
} else {
per_slot_offsets = bld.vgrf(BRW_REGISTER_TYPE_UD);
per_slot_offsets = bld.vgrf(BRW_TYPE_UD);
bld.MUL(per_slot_offsets, gs_vertex_count,
brw_imm_ud(output_vertex_size));
}
@ -762,7 +762,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
}
fs_reg zero(VGRF, alloc.allocate(dispatch_width / 8),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
bld.MOV(zero, brw_imm_ud(0u));
if (vue_map->slots_valid & VARYING_BIT_PRIMITIVE_SHADING_RATE &&
@ -771,7 +771,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
} else if (devinfo->has_coarse_pixel_primitive_and_cb) {
uint32_t one_fp16 = 0x3C00;
fs_reg one_by_one_fp16(VGRF, alloc.allocate(dispatch_width / 8),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
bld.MOV(one_by_one_fp16, brw_imm_ud((one_fp16 << 16) | one_fp16));
sources[length++] = one_by_one_fp16;
} else {
@ -846,7 +846,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = per_slot_offsets;
srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF,
alloc.allocate((dispatch_width / 8) * length),
BRW_REGISTER_TYPE_F);
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length);
abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0);
@ -886,9 +886,9 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
return;
fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
fs_reg payload = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
bld.exec_all().MOV(uniform_urb_handle, urb_handle);
@ -912,9 +912,9 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
*/
if (devinfo->ver == 11 && stage == MESA_SHADER_TESS_EVAL) {
assert(dispatch_width == 8);
fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
fs_reg uniform_mask = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
fs_reg payload = fs_reg(VGRF, alloc.allocate(4), BRW_REGISTER_TYPE_UD);
fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(1), BRW_TYPE_UD);
fs_reg uniform_mask = fs_reg(VGRF, alloc.allocate(1), BRW_TYPE_UD);
fs_reg payload = fs_reg(VGRF, alloc.allocate(4), BRW_TYPE_UD);
/* Workaround requires all 8 channels (lanes) to be valid. This is
* understood to mean they all need to be alive. First trick is to find
@ -960,7 +960,7 @@ void
fs_visitor::emit_urb_fence()
{
const fs_builder bld = fs_builder(this).at_end();
fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg dst = bld.vgrf(BRW_TYPE_UD);
fs_inst *fence = bld.emit(SHADER_OPCODE_MEMORY_FENCE, dst,
brw_vec8_grf(0, 0),
brw_imm_ud(true),
@ -984,9 +984,9 @@ fs_visitor::emit_cs_terminate()
* g112-127. So, copy it to a virtual register, The register allocator will
* make sure it uses the appropriate register range.
*/
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD);
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_TYPE_UD);
fs_reg payload = fs_reg(VGRF, alloc.allocate(reg_unit(devinfo)),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
ubld.group(8 * reg_unit(devinfo), 0).MOV(payload, g0);
/* Set the descriptor to "Dereference Resource" and "Root Thread" */

4
src/intel/compiler/brw_fs_workaround.cpp
View file

@ -103,7 +103,7 @@ brw_fs_workaround_memory_fence_before_eot(fs_visitor &s)
const fs_builder ibld(&s, block, inst);
const fs_builder ubld = ibld.exec_all().group(1, 0);
fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg dst = ubld.vgrf(BRW_TYPE_UD);
fs_inst *dummy_fence = ubld.emit(SHADER_OPCODE_MEMORY_FENCE,
dst, brw_vec8_grf(0, 0),
/* commit enable */ brw_imm_ud(1),
@ -230,7 +230,7 @@ brw_fs_workaround_nomask_control_flow(fs_visitor &s)
const fs_builder ubld = fs_builder(&s, block, inst)
.exec_all().group(s.dispatch_width, 0);
const fs_reg flag = retype(brw_flag_reg(0, 0),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
/* Due to the lack of flag register allocation we need to save
* and restore the flag register if it's live.

74
src/intel/compiler/brw_gram.y
View file

@ -948,7 +948,7 @@ sendinstruction:
brw_inst_set_bits(brw_last_inst, 127, 96, $6);
brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
BRW_IMMEDIATE_VALUE,
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
// TODO: set instruction group instead of qtr and nib ctrl
@ -1133,7 +1133,7 @@ branchinstruction:
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
BRW_TYPE_D));
if (p->devinfo->ver < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0));
}
@ -1148,7 +1148,7 @@ branchinstruction:
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
BRW_TYPE_D)));
if (p->devinfo->ver < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
@ -1168,7 +1168,7 @@ breakinstruction:
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
BRW_TYPE_D));
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
brw_pop_insn_state(p);
@ -1183,7 +1183,7 @@ breakinstruction:
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
BRW_TYPE_D));
if (p->devinfo->ver < 12) {
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
@ -1219,7 +1219,7 @@ loopinstruction:
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
BRW_TYPE_D));
if (p->devinfo->ver < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
@ -1348,7 +1348,7 @@ dstoperandex:
{
$$ = $1;
$$.hstride = 1;
$$.type = BRW_REGISTER_TYPE_UW;
$$.type = BRW_TYPE_UW;
}
;
@ -1388,44 +1388,44 @@ immreg:
immval imm_type
{
switch ($2) {
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_UD:
$$ = brw_imm_ud($1);
break;
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
$$ = brw_imm_d($1);
break;
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_UW:
$$ = brw_imm_uw($1 | ($1 << 16));
break;
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_W:
$$ = brw_imm_w($1);
break;
case BRW_REGISTER_TYPE_F:
$$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
case BRW_TYPE_F:
$$ = brw_imm_reg(BRW_TYPE_F);
/* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
$$.u64 = $1;
break;
case BRW_REGISTER_TYPE_V:
case BRW_TYPE_V:
$$ = brw_imm_v($1);
break;
case BRW_REGISTER_TYPE_UV:
case BRW_TYPE_UV:
$$ = brw_imm_uv($1);
break;
case BRW_REGISTER_TYPE_VF:
case BRW_TYPE_VF:
$$ = brw_imm_vf($1);
break;
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_Q:
$$ = brw_imm_q($1);
break;
case BRW_REGISTER_TYPE_UQ:
case BRW_TYPE_UQ:
$$ = brw_imm_uq($1);
break;
case BRW_REGISTER_TYPE_DF:
$$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
case BRW_TYPE_DF:
$$ = brw_imm_reg(BRW_TYPE_DF);
$$.d64 = $1;
break;
case BRW_REGISTER_TYPE_HF:
$$ = brw_imm_reg(BRW_REGISTER_TYPE_HF);
case BRW_TYPE_HF:
$$ = brw_imm_reg(BRW_TYPE_HF);
$$.ud = $1 | ($1 << 16);
break;
default:
@ -1500,7 +1500,7 @@ srcarcoperandex:
}
| threadcontrolreg
{
$$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
$$ = set_direct_src_operand(&$1, BRW_TYPE_UW);
}
;
@ -1864,24 +1864,24 @@ region_wh:
;
reg_type:
TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
| TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
| TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
| TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
| TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
| TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
| TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
| TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
| TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
| TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
| TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
TYPE_F { $$ = BRW_TYPE_F; }
| TYPE_UD { $$ = BRW_TYPE_UD; }
| TYPE_D { $$ = BRW_TYPE_D; }
| TYPE_UW { $$ = BRW_TYPE_UW; }
| TYPE_W { $$ = BRW_TYPE_W; }
| TYPE_UB { $$ = BRW_TYPE_UB; }
| TYPE_B { $$ = BRW_TYPE_B; }
| TYPE_DF { $$ = BRW_TYPE_DF; }
| TYPE_UQ { $$ = BRW_TYPE_UQ; }
| TYPE_Q { $$ = BRW_TYPE_Q; }
| TYPE_HF { $$ = BRW_TYPE_HF; }
;
imm_type:
reg_type { $$ = $1; }
| TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
| TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
| TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
| TYPE_V { $$ = BRW_TYPE_V; }
| TYPE_VF { $$ = BRW_TYPE_VF; }
| TYPE_UV { $$ = BRW_TYPE_UV; }
;
writemask:

24
src/intel/compiler/brw_ir_fs.h
View file

@ -293,9 +293,9 @@ is_periodic(const fs_reg &reg, unsigned n)
return true;
} else if (reg.file == IMM) {
const unsigned period = (reg.type == BRW_REGISTER_TYPE_UV ||
reg.type == BRW_REGISTER_TYPE_V ? 8 :
reg.type == BRW_REGISTER_TYPE_VF ? 4 :
const unsigned period = (reg.type == BRW_TYPE_UV ||
reg.type == BRW_TYPE_V ? 8 :
reg.type == BRW_TYPE_VF ? 4 :
1);
return n % period == 0;
@ -651,7 +651,7 @@ regs_read(const fs_inst *inst, unsigned i)
static inline enum brw_reg_type
get_exec_type(const fs_inst *inst)
{
brw_reg_type exec_type = BRW_REGISTER_TYPE_B;
brw_reg_type exec_type = BRW_TYPE_B;
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].file != BAD_FILE &&
@ -665,10 +665,10 @@ get_exec_type(const fs_inst *inst)
}
}
if (exec_type == BRW_REGISTER_TYPE_B)
if (exec_type == BRW_TYPE_B)
exec_type = inst->dst.type;
assert(exec_type != BRW_REGISTER_TYPE_B);
assert(exec_type != BRW_TYPE_B);
/* Promotion of the execution type to 32-bit for conversions from or to
* half-float seems to be consistent with the following text from the
@ -685,10 +685,10 @@ get_exec_type(const fs_inst *inst)
*/
if (type_sz(exec_type) == 2 &&
inst->dst.type != exec_type) {
if (exec_type == BRW_REGISTER_TYPE_HF)
exec_type = BRW_REGISTER_TYPE_F;
else if (inst->dst.type == BRW_REGISTER_TYPE_HF)
exec_type = BRW_REGISTER_TYPE_D;
if (exec_type == BRW_TYPE_HF)
exec_type = BRW_TYPE_F;
else if (inst->dst.type == BRW_TYPE_HF)
exec_type = BRW_TYPE_D;
}
return exec_type;
@ -716,8 +716,8 @@ is_unordered(const intel_device_info *devinfo, const fs_inst *inst)
return is_send(inst) || (devinfo->ver < 20 && inst->is_math()) ||
inst->opcode == BRW_OPCODE_DPAS ||
(devinfo->has_64bit_float_via_math_pipe &&
(get_exec_type(inst) == BRW_REGISTER_TYPE_DF ||
inst->dst.type == BRW_REGISTER_TYPE_DF));
(get_exec_type(inst) == BRW_TYPE_DF ||
inst->dst.type == BRW_TYPE_DF));
}
/*

2
src/intel/compiler/brw_ir_performance.cpp
View file

@ -144,7 +144,7 @@ namespace {
if ((inst->opcode == BRW_OPCODE_MUL || inst->opcode == BRW_OPCODE_MAD) &&
!brw_reg_type_is_floating_point(tx) && type_sz(tx) == 4 &&
type_sz(inst->src[0].type) == type_sz(inst->src[1].type))
tx = brw_int_type(8, tx == BRW_REGISTER_TYPE_D);
tx = brw_int_type(8, tx == BRW_TYPE_D);
rcount = inst->opcode == BRW_OPCODE_DPAS ? inst->rcount : 0;
}

162
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -48,7 +48,7 @@ lower_urb_read_logical_send(const fs_builder &bld, fs_inst *inst)
payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS];
fs_reg payload = fs_reg(VGRF, bld.shader->alloc.allocate(header_size),
BRW_REGISTER_TYPE_F);
BRW_TYPE_F);
bld.LOAD_PAYLOAD(payload, payload_sources, header_size, header_size);
inst->opcode = SHADER_OPCODE_SEND;
@ -89,7 +89,7 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
/* Calculate the total number of components of the payload. */
const unsigned dst_comps = inst->size_written / (REG_SIZE * reg_unit(devinfo));
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg payload = bld.vgrf(BRW_TYPE_UD);
bld.MOV(payload, handle);
@ -149,7 +149,7 @@ lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst)
fs_reg *payload_sources = new fs_reg[length];
fs_reg payload = fs_reg(VGRF, bld.shader->alloc.allocate(length),
BRW_REGISTER_TYPE_F);
BRW_TYPE_F);
unsigned header_size = 0;
payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_HANDLE];
@ -206,7 +206,7 @@ lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
const unsigned src_comps = MAX2(1, inst->components_read(URB_LOGICAL_SRC_DATA));
const unsigned src_sz = type_sz(src.type);
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg payload = bld.vgrf(BRW_TYPE_UD);
bld.MOV(payload, handle);
@ -228,7 +228,7 @@ lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
if (cmask.file != BAD_FILE) {
assert(cmask.file == IMM);
assert(cmask.type == BRW_REGISTER_TYPE_UD);
assert(cmask.type == BRW_TYPE_UD);
mask = cmask.ud >> 16;
}
@ -268,8 +268,8 @@ setup_color_payload(const fs_builder &bld, const brw_wm_prog_key *key,
fs_reg *dst, fs_reg color, unsigned components)
{
if (key->clamp_fragment_color) {
fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, 4);
assert(color.type == BRW_REGISTER_TYPE_F);
fs_reg tmp = bld.vgrf(BRW_TYPE_F, 4);
assert(color.type == BRW_TYPE_F);
for (unsigned i = 0; i < components; i++)
set_saturate(true,
@ -319,17 +319,17 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
*/
const fs_builder ubld = bld.exec_all().group(8, 0);
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
fs_reg header = ubld.vgrf(BRW_TYPE_UD, 2);
if (bld.group() < 16) {
/* The header starts off as g0 and g1 for the first half */
ubld.group(16, 0).MOV(header, retype(brw_vec8_grf(0, 0),
BRW_REGISTER_TYPE_UD));
BRW_TYPE_UD));
} else {
/* The header starts off as g0 and g2 for the second half */
assert(bld.group() < 32);
const fs_reg header_sources[2] = {
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD),
retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD),
retype(brw_vec8_grf(0, 0), BRW_TYPE_UD),
retype(brw_vec8_grf(2, 0), BRW_TYPE_UD),
};
ubld.LOAD_PAYLOAD(header, header_sources, 2, 0);
@ -353,7 +353,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
/* OR extra bits into g0.0 */
ubld.group(1, 0).OR(component(header, 0),
retype(brw_vec1_grf(0, 0),
BRW_REGISTER_TYPE_UD),
BRW_TYPE_UD),
brw_imm_ud(g00_bits));
}
@ -364,7 +364,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
if (prog_data->uses_kill) {
ubld.group(1, 0).MOV(retype(component(header, 15),
BRW_REGISTER_TYPE_UW),
BRW_TYPE_UW),
brw_sample_mask_reg(bld));
}
@ -389,7 +389,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
for (unsigned i = 0; i < bld.dispatch_width() / 8; i++) {
const fs_builder &ubld = bld.exec_all().group(8, i)
.annotate("FB write src0 alpha");
const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_F);
const fs_reg tmp = ubld.vgrf(BRW_TYPE_F);
ubld.MOV(tmp, horiz_offset(src0_alpha, i * 8));
setup_color_payload(ubld, key, &sources[length], tmp, 1);
length++;
@ -398,7 +398,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
if (sample_mask.file != BAD_FILE) {
const fs_reg tmp(VGRF, bld.shader->alloc.allocate(reg_unit(devinfo)),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
/* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
* relevant. Since it's unsigned single words one vgrf is always
@ -407,11 +407,11 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
* selected the subspans for the first or second half respectively.
*/
assert(sample_mask.file != BAD_FILE && type_sz(sample_mask.type) == 4);
sample_mask.type = BRW_REGISTER_TYPE_UW;
sample_mask.type = BRW_TYPE_UW;
sample_mask.stride *= 2;
bld.exec_all().annotate("FB write oMask")
.MOV(horiz_offset(retype(tmp, BRW_REGISTER_TYPE_UW),
.MOV(horiz_offset(retype(tmp, BRW_TYPE_UW),
inst->group % (16 * reg_unit(devinfo))),
sample_mask);
@ -448,15 +448,15 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
*/
assert(length < 15 * reg_unit(devinfo));
sources[length] = bld.vgrf(BRW_REGISTER_TYPE_UD);
sources[length] = bld.vgrf(BRW_TYPE_UD);
bld.exec_all().annotate("FB write OS")
.MOV(retype(sources[length], BRW_REGISTER_TYPE_UB),
subscript(src_stencil, BRW_REGISTER_TYPE_UB, 0));
.MOV(retype(sources[length], BRW_TYPE_UB),
subscript(src_stencil, BRW_TYPE_UB, 0));
length++;
}
/* Send from the GRF */
fs_reg payload = fs_reg(VGRF, -1, BRW_REGISTER_TYPE_F);
fs_reg payload = fs_reg(VGRF, -1, BRW_TYPE_F);
fs_inst *load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size);
payload.nr = bld.shader->alloc.allocate(regs_written(load));
load->dst = payload;
@ -475,7 +475,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
} else if (prog_data->coarse_pixel_dispatch == BRW_SOMETIMES) {
STATIC_ASSERT(INTEL_MSAA_FLAG_COARSE_RT_WRITES == (1 << 18));
const fs_builder &ubld = bld.exec_all().group(8, 0);
desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
desc = ubld.vgrf(BRW_TYPE_UD);
ubld.AND(desc, dynamic_msaa_flags(prog_data),
brw_imm_ud(INTEL_MSAA_FLAG_COARSE_RT_WRITES));
desc = component(desc, 0);
@ -520,18 +520,18 @@ lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst,
const intel_device_info *devinfo = bld.shader->devinfo;
const fs_builder &ubld = bld.exec_all().group(8, 0);
const unsigned length = 2;
const fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, length);
const fs_reg header = ubld.vgrf(BRW_TYPE_UD, length);
assert(devinfo->ver >= 9 && devinfo->ver < 20);
if (bld.group() < 16) {
ubld.group(16, 0).MOV(header, retype(brw_vec8_grf(0, 0),
BRW_REGISTER_TYPE_UD));
BRW_TYPE_UD));
} else {
assert(bld.group() < 32);
const fs_reg header_sources[] = {
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD),
retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD)
retype(brw_vec8_grf(0, 0), BRW_TYPE_UD),
retype(brw_vec8_grf(2, 0), BRW_TYPE_UD)
};
ubld.LOAD_PAYLOAD(header, header_sources, ARRAY_SIZE(header_sources), 0);
@ -545,7 +545,7 @@ lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst,
* r1.1 in order to fix things up.
*/
ubld.group(1, 0).MOV(component(header, 9),
retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_UD));
retype(brw_vec1_grf(1, 1), BRW_TYPE_UD));
}
}
@ -695,7 +695,7 @@ emit_load_payload_with_padding(const fs_builder &bld, const fs_reg &dst,
retype(dst, src[i].type).component_size(bld.dispatch_width());
const enum brw_reg_type padding_payload_type =
brw_reg_type_from_bit_size(type_sz(src[i].type) * 8,
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
src_comps[length++] = src[i];
@ -756,11 +756,11 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
const brw_compiler *compiler = bld.shader->compiler;
const intel_device_info *devinfo = bld.shader->devinfo;
const enum brw_reg_type payload_type =
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_F);
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_TYPE_F);
const enum brw_reg_type payload_unsigned_type =
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_UD);
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_TYPE_UD);
const enum brw_reg_type payload_signed_type =
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_D);
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_TYPE_D);
unsigned reg_width = bld.dispatch_width() / 8;
unsigned header_size = 0, length = 0;
opcode op = inst->opcode;
@ -784,7 +784,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
* larger sampler numbers we need to offset the Sampler State Pointer in
* the header.
*/
fs_reg header = retype(sources[0], BRW_REGISTER_TYPE_UD);
fs_reg header = retype(sources[0], BRW_TYPE_UD);
for (header_size = 0; header_size < reg_unit(devinfo); header_size++)
sources[length++] = byte_offset(header, REG_SIZE * header_size);
@ -808,7 +808,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
if (devinfo->ver >= 11)
ubld.MOV(header, brw_imm_ud(0));
else
ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_TYPE_UD));
if (inst->offset) {
ubld1.MOV(component(header, 2), brw_imm_ud(inst->offset));
} else if (devinfo->ver < 11 &&
@ -843,15 +843,15 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
}
} else if (is_high_sampler(devinfo, sampler)) {
fs_reg sampler_state_ptr =
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD);
retype(brw_vec1_grf(0, 3), BRW_TYPE_UD);
/* Gfx11+ sampler message headers include bits in 4:0 which conflict
* with the ones included in g0.3 bits 4:0. Mask them out.
*/
if (devinfo->ver >= 11) {
sampler_state_ptr = ubld1.vgrf(BRW_REGISTER_TYPE_UD);
sampler_state_ptr = ubld1.vgrf(BRW_TYPE_UD);
ubld1.AND(sampler_state_ptr,
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 3), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 5)));
}
@ -862,7 +862,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
ubld1.ADD(component(header, 3), sampler_state_ptr,
brw_imm_ud(16 * (sampler.ud / 16) * sampler_state_size));
} else {
fs_reg tmp = ubld1.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg tmp = ubld1.vgrf(BRW_TYPE_UD);
ubld1.AND(tmp, sampler, brw_imm_ud(0x0f0));
ubld1.SHL(tmp, tmp, brw_imm_ud(4));
ubld1.ADD(component(header, 3), sampler_state_ptr, tmp);
@ -872,7 +872,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
* with the ones included in g0.3 bits 4:0. Mask them out.
*/
ubld1.AND(component(header, 3),
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 3), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 5)));
}
}
@ -1083,7 +1083,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
const fs_reg src_payload =
fs_reg(VGRF, bld.shader->alloc.allocate(length * reg_width),
BRW_REGISTER_TYPE_F);
BRW_TYPE_F);
/* In case of 16-bit payload each component takes one full register in
* both SIMD8H and SIMD16H modes. In both cases one reg can hold 16
* elements. In SIMD8H case hardware simply expects the components to be
@ -1143,7 +1143,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
inst->src[0] = brw_imm_ud(0);
} else {
const fs_builder ubld = bld.group(1, 0).exec_all();
fs_reg desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg desc = ubld.vgrf(BRW_TYPE_UD);
ubld.SHL(desc, sampler, brw_imm_ud(8));
inst->src[0] = component(desc, 0);
}
@ -1151,7 +1151,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
/* We assume that the driver provided the handle in the top 20 bits so
* we can use the surface handle directly as the extended descriptor.
*/
inst->src[1] = retype(surface_handle, BRW_REGISTER_TYPE_UD);
inst->src[1] = retype(surface_handle, BRW_TYPE_UD);
inst->send_ex_bso = compiler->extended_bindless_surface_offset;
} else {
/* Immediate portion of the descriptor */
@ -1162,7 +1162,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
simd_mode,
0 /* return_format unused on gfx7+ */);
const fs_builder ubld = bld.group(1, 0).exec_all();
fs_reg desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg desc = ubld.vgrf(BRW_TYPE_UD);
if (surface.equals(sampler)) {
/* This case is common in GL */
ubld.MUL(desc, surface, brw_imm_ud(0x101));
@ -1308,7 +1308,7 @@ emit_predicate_on_vector_mask(const fs_builder &bld, fs_inst *inst)
const fs_builder ubld = bld.exec_all().group(1, 0);
const fs_visitor &s = *bld.shader;
const fs_reg vector_mask = ubld.vgrf(BRW_REGISTER_TYPE_UW);
const fs_reg vector_mask = ubld.vgrf(BRW_TYPE_UW);
ubld.UNDEF(vector_mask);
ubld.emit(SHADER_OPCODE_READ_SR_REG, vector_mask, brw_imm_ud(3));
const unsigned subreg = sample_mask_flag_subreg(s);
@ -1352,12 +1352,12 @@ setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc,
/* We assume that the driver provided the handle in the top 20 bits so
* we can use the surface handle directly as the extended descriptor.
*/
inst->src[1] = retype(surface_handle, BRW_REGISTER_TYPE_UD);
inst->src[1] = retype(surface_handle, BRW_TYPE_UD);
inst->send_ex_bso = compiler->extended_bindless_surface_offset;
} else {
inst->desc = desc;
const fs_builder ubld = bld.exec_all().group(1, 0);
fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg tmp = ubld.vgrf(BRW_TYPE_UD);
ubld.AND(tmp, surface, brw_imm_ud(0xff));
inst->src[0] = component(tmp, 0);
inst->src[1] = brw_imm_ud(0); /* ex_desc */
@ -1383,7 +1383,7 @@ setup_lsc_surface_descriptors(const fs_builder &bld, fs_inst *inst,
/* We assume that the driver provided the handle in the top 20 bits so
* we can use the surface handle directly as the extended descriptor.
*/
inst->src[1] = retype(surface, BRW_REGISTER_TYPE_UD);
inst->src[1] = retype(surface, BRW_TYPE_UD);
break;
case LSC_ADDR_SURFTYPE_BTI:
@ -1392,7 +1392,7 @@ setup_lsc_surface_descriptors(const fs_builder &bld, fs_inst *inst,
inst->src[1] = brw_imm_ud(lsc_bti_ex_desc(devinfo, surface.ud));
} else {
const fs_builder ubld = bld.exec_all().group(1, 0);
fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg tmp = ubld.vgrf(BRW_TYPE_UD);
ubld.SHL(tmp, surface, brw_imm_ud(24));
inst->src[1] = component(tmp, 0);
}
@ -1452,7 +1452,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
if (is_stateless) {
assert(!is_surface_access);
fs_builder ubld = bld.exec_all().group(8, 0);
header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
header = ubld.vgrf(BRW_TYPE_UD);
ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header);
}
const unsigned header_sz = header.file != BAD_FILE ? 1 : 0;
@ -1476,7 +1476,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
} else {
/* Allocate space for the payload. */
const unsigned sz = header_sz + addr_sz + src_sz;
payload = bld.vgrf(BRW_REGISTER_TYPE_UD, sz);
payload = bld.vgrf(BRW_TYPE_UD, sz);
fs_reg *const components = new fs_reg[sz];
unsigned n = 0;
@ -1855,16 +1855,16 @@ lower_lsc_block_logical_send(const fs_builder &bld, fs_inst *inst)
fs_builder ubld = bld.exec_all().group(1, 0);
fs_reg stateless_ex_desc;
if (is_stateless) {
stateless_ex_desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
stateless_ex_desc = ubld.vgrf(BRW_TYPE_UD);
ubld.AND(stateless_ex_desc,
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 5), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 10)));
}
fs_reg data;
if (write) {
const unsigned src_sz = inst->components_read(SURFACE_LOGICAL_SRC_DATA);
data = retype(bld.move_to_vgrf(src, src_sz), BRW_REGISTER_TYPE_UD);
data = retype(bld.move_to_vgrf(src, src_sz), BRW_TYPE_UD);
}
inst->opcode = SHADER_OPCODE_SEND;
@ -1939,7 +1939,7 @@ lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst)
/* The address is stored in the header. See MH_A32_GO and MH_BTS_GO. */
fs_builder ubld = bld.exec_all().group(8, 0);
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg header = ubld.vgrf(BRW_TYPE_UD);
if (is_stateless)
ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header);
@ -1956,7 +1956,7 @@ lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst)
unsigned ex_mlen = 0;
if (write) {
const unsigned src_sz = inst->components_read(SURFACE_LOGICAL_SRC_DATA);
data = retype(bld.move_to_vgrf(src, src_sz), BRW_REGISTER_TYPE_UD);
data = retype(bld.move_to_vgrf(src, src_sz), BRW_TYPE_UD);
ex_mlen = src_sz * type_sz(src.type) * inst->exec_size / REG_SIZE;
}
@ -1989,17 +1989,17 @@ emit_a64_oword_block_header(const fs_builder &bld, const fs_reg &addr)
fs_reg expanded_addr = addr;
if (addr.file == UNIFORM) {
/* We can't do stride 1 with the UNIFORM file, it requires stride 0 */
expanded_addr = ubld.vgrf(BRW_REGISTER_TYPE_UQ);
expanded_addr = ubld.vgrf(BRW_TYPE_UQ);
expanded_addr.stride = 0;
ubld.MOV(expanded_addr, retype(addr, BRW_REGISTER_TYPE_UQ));
ubld.MOV(expanded_addr, retype(addr, BRW_TYPE_UQ));
}
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg header = ubld.vgrf(BRW_TYPE_UD);
ubld.MOV(header, brw_imm_ud(0));
/* Use a 2-wide MOV to fill out the address */
fs_reg addr_vec2 = expanded_addr;
addr_vec2.type = BRW_REGISTER_TYPE_UD;
addr_vec2.type = BRW_TYPE_UD;
addr_vec2.stride = 1;
ubld.group(2, 0).MOV(header, addr_vec2);
@ -2042,9 +2042,9 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst)
const unsigned arg = inst->src[A64_LOGICAL_ARG].ud;
const bool has_side_effects = inst->has_side_effects();
fs_reg payload = retype(bld.move_to_vgrf(addr, 1), BRW_REGISTER_TYPE_UD);
fs_reg payload = retype(bld.move_to_vgrf(addr, 1), BRW_TYPE_UD);
fs_reg payload2 = retype(bld.move_to_vgrf(src, src_comps),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
unsigned ex_mlen = src_comps * src_sz * inst->exec_size / REG_SIZE;
unsigned num_components = 0;
bool has_dest = false;
@ -2187,15 +2187,15 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst)
if (inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL) {
ex_mlen = src_comps * type_sz(src.type) * inst->exec_size / REG_SIZE;
payload2 = retype(bld.move_to_vgrf(src, src_comps),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
}
} else {
/* On Skylake and above, we have SENDS */
mlen = 2 * (inst->exec_size / 8);
ex_mlen = src_comps * type_sz(src.type) * inst->exec_size / REG_SIZE;
payload = retype(bld.move_to_vgrf(addr, 1), BRW_REGISTER_TYPE_UD);
payload = retype(bld.move_to_vgrf(addr, 1), BRW_TYPE_UD);
payload2 = retype(bld.move_to_vgrf(src, src_comps),
BRW_REGISTER_TYPE_UD);
BRW_TYPE_UD);
}
uint32_t desc;
@ -2363,7 +2363,7 @@ lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld,
bld.emit(*inst);
/* Offset the source */
inst->src[2] = bld.vgrf(BRW_REGISTER_TYPE_UD);
inst->src[2] = bld.vgrf(BRW_TYPE_UD);
bld.ADD(inst->src[2], ubo_offset, brw_imm_ud(c * 4));
/* Offset the destination */
@ -2386,7 +2386,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
* send-from-grf instruction. Since sends can't handle strides or
* source modifiers, we have to make a copy of the offset source.
*/
fs_reg ubo_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg ubo_offset = bld.vgrf(BRW_TYPE_UD);
bld.MOV(ubo_offset, offset_B);
assert(inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT].file == BRW_IMMEDIATE_VALUE);
@ -2441,7 +2441,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
bld.emit(*inst);
/* Offset the source */
inst->src[2] = bld.vgrf(BRW_REGISTER_TYPE_UD);
inst->src[2] = bld.vgrf(BRW_TYPE_UD);
bld.ADD(inst->src[2], ubo_offset, brw_imm_ud(c * 4));
/* Offset the destination */
@ -2503,7 +2503,7 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst,
STATIC_ASSERT(INTEL_MSAA_FLAG_COARSE_PI_MSG == (1 << 15));
fs_reg orig_desc = desc;
const fs_builder &ubld = bld.exec_all().group(8, 0);
desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
desc = ubld.vgrf(BRW_TYPE_UD);
ubld.AND(desc, dynamic_msaa_flags(wm_prog_data),
brw_imm_ud(INTEL_MSAA_FLAG_COARSE_PI_MSG));
@ -2533,7 +2533,7 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst,
if (dynamic_mode) {
fs_reg orig_desc = desc;
const fs_builder &ubld = bld.exec_all().group(8, 0);
desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
desc = ubld.vgrf(BRW_TYPE_UD);
/* The predicate should have been built in brw_fs_nir.cpp when emitting
* NIR code. This guarantees that we do not have incorrect interactions
@ -2584,13 +2584,13 @@ lower_btd_logical_send(const fs_builder &bld, fs_inst *inst)
const unsigned unit = reg_unit(devinfo);
const unsigned mlen = 2 * unit;
const fs_builder ubld = bld.exec_all();
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2 * unit);
fs_reg header = ubld.vgrf(BRW_TYPE_UD, 2 * unit);
ubld.MOV(header, brw_imm_ud(0));
switch (inst->opcode) {
case SHADER_OPCODE_BTD_SPAWN_LOGICAL:
assert(type_sz(global_addr.type) == 8 && global_addr.stride == 0);
global_addr.type = BRW_REGISTER_TYPE_UD;
global_addr.type = BRW_TYPE_UD;
global_addr.stride = 1;
ubld.group(2, 0).MOV(header, global_addr);
break;
@ -2607,9 +2607,9 @@ lower_btd_logical_send(const fs_builder &bld, fs_inst *inst)
/* Stack IDs are always in R1 regardless of whether we're coming from a
* bindless shader or a regular compute shader.
*/
fs_reg stack_ids = retype(offset(header, bld, 1), BRW_REGISTER_TYPE_UW);
fs_reg stack_ids = retype(offset(header, bld, 1), BRW_TYPE_UW);
bld.exec_all().MOV(stack_ids, retype(brw_vec8_grf(1 * unit, 0),
BRW_REGISTER_TYPE_UW));
BRW_TYPE_UW));
unsigned ex_mlen = 0;
fs_reg payload;
@ -2655,7 +2655,7 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst)
* so that the MOV operates on 2 components rather than twice the same
* component.
*/
fs_reg globals_addr = retype(inst->src[RT_LOGICAL_SRC_GLOBALS], BRW_REGISTER_TYPE_UD);
fs_reg globals_addr = retype(inst->src[RT_LOGICAL_SRC_GLOBALS], BRW_TYPE_UD);
globals_addr.stride = 1;
const fs_reg bvh_level =
inst->src[RT_LOGICAL_SRC_BVH_LEVEL].file == BRW_IMMEDIATE_VALUE ?
@ -2674,14 +2674,14 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst)
const unsigned unit = reg_unit(devinfo);
const unsigned mlen = unit;
const fs_builder ubld = bld.exec_all();
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg header = ubld.vgrf(BRW_TYPE_UD);
ubld.MOV(header, brw_imm_ud(0));
ubld.group(2, 0).MOV(header, globals_addr);
if (synchronous)
ubld.group(1, 0).MOV(byte_offset(header, 16), brw_imm_ud(synchronous));
const unsigned ex_mlen = inst->exec_size / 8;
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg payload = bld.vgrf(BRW_TYPE_UD);
if (bvh_level.file == BRW_IMMEDIATE_VALUE &&
trace_ray_control.file == BRW_IMMEDIATE_VALUE) {
bld.MOV(payload, brw_imm_ud(SET_BITS(trace_ray_control.ud, 9, 8) |
@ -2700,8 +2700,8 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst)
* payload register.
*/
if (!synchronous) {
bld.AND(subscript(payload, BRW_REGISTER_TYPE_UW, 1),
retype(brw_vec8_grf(1 * unit, 0), BRW_REGISTER_TYPE_UW),
bld.AND(subscript(payload, BRW_TYPE_UW, 1),
retype(brw_vec8_grf(1 * unit, 0), BRW_TYPE_UW),
brw_imm_uw(0x7ff));
}
@ -2752,7 +2752,7 @@ lower_get_buffer_size(const fs_builder &bld, fs_inst *inst)
BRW_SAMPLER_SIMD_MODE_SIMD8,
return_format);
inst->dst = retype(inst->dst, BRW_REGISTER_TYPE_UW);
inst->dst = retype(inst->dst, BRW_TYPE_UW);
inst->sfid = BRW_SFID_SAMPLER;
setup_surface_descriptors(bld, inst, desc, surface, surface_handle);
}
@ -2940,7 +2940,7 @@ brw_fs_lower_uniform_pull_constant_loads(fs_visitor &s)
const fs_builder ubld =
fs_builder(&s, block, inst).group(8, 0).exec_all();
const fs_reg payload = ubld.vgrf(BRW_REGISTER_TYPE_UD);
const fs_reg payload = ubld.vgrf(BRW_TYPE_UD);
ubld.MOV(payload, offset_B);
inst->sfid = GFX12_SFID_UGM;
@ -2976,10 +2976,10 @@ brw_fs_lower_uniform_pull_constant_loads(fs_visitor &s)
s.invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
} else {
const fs_builder ubld = fs_builder(&s, block, inst).exec_all();
fs_reg header = fs_builder(&s, 8).exec_all().vgrf(BRW_REGISTER_TYPE_UD);
fs_reg header = fs_builder(&s, 8).exec_all().vgrf(BRW_TYPE_UD);
ubld.group(8, 0).MOV(header,
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
retype(brw_vec8_grf(0, 0), BRW_TYPE_UD));
ubld.group(1, 0).MOV(component(header, 2),
brw_imm_ud(offset_B.ud / 16));

24
src/intel/compiler/brw_nir.c
View file

@ -2043,36 +2043,36 @@ brw_type_for_nir_type(const struct intel_device_info *devinfo,
switch (type) {
case nir_type_uint:
case nir_type_uint32:
return BRW_REGISTER_TYPE_UD;
return BRW_TYPE_UD;
case nir_type_bool:
case nir_type_int:
case nir_type_bool32:
case nir_type_int32:
return BRW_REGISTER_TYPE_D;
return BRW_TYPE_D;
case nir_type_float:
case nir_type_float32:
return BRW_REGISTER_TYPE_F;
return BRW_TYPE_F;
case nir_type_float16:
return BRW_REGISTER_TYPE_HF;
return BRW_TYPE_HF;
case nir_type_float64:
return BRW_REGISTER_TYPE_DF;
return BRW_TYPE_DF;
case nir_type_int64:
return BRW_REGISTER_TYPE_Q;
return BRW_TYPE_Q;
case nir_type_uint64:
return BRW_REGISTER_TYPE_UQ;
return BRW_TYPE_UQ;
case nir_type_int16:
return BRW_REGISTER_TYPE_W;
return BRW_TYPE_W;
case nir_type_uint16:
return BRW_REGISTER_TYPE_UW;
return BRW_TYPE_UW;
case nir_type_int8:
return BRW_REGISTER_TYPE_B;
return BRW_TYPE_B;
case nir_type_uint8:
return BRW_REGISTER_TYPE_UB;
return BRW_TYPE_UB;
default:
unreachable("unknown type");
}
return BRW_REGISTER_TYPE_F;
return BRW_TYPE_F;
}
nir_shader *

118
src/intel/compiler/brw_reg.h
View file

@ -236,35 +236,35 @@ brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b)
return false;
switch ((enum brw_reg_type) a->type) {
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_UQ:
case BRW_TYPE_Q:
return a->d64 == -b->d64;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
return a->df == -b->df;
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_UD:
case BRW_TYPE_D:
return a->d == -b->d;
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
return a->f == -b->f;
case BRW_REGISTER_TYPE_VF:
case BRW_TYPE_VF:
/* It is tempting to treat 0 as a negation of 0 (and -0 as a negation
* of -0). There are occasions where 0 or -0 is used and the exact
* bit pattern is desired. At the very least, changing this to allow
* 0 as a negation of 0 causes some fp64 tests to fail on IVB.
*/
return a->ud == (b->ud ^ 0x80808080);
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_V:
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_UW:
case BRW_TYPE_W:
case BRW_TYPE_UV:
case BRW_TYPE_V:
case BRW_TYPE_HF:
/* FINISHME: Implement support for these types once there is
* something in the compiler that can generate them. Until then,
* they cannot be tested.
*/
return false;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case BRW_TYPE_UB:
case BRW_TYPE_B:
default:
unreachable("not reached");
}
@ -294,14 +294,14 @@ static inline enum brw_reg_type
get_exec_type(const enum brw_reg_type type)
{
switch (type) {
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_V:
return BRW_REGISTER_TYPE_W;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_UV:
return BRW_REGISTER_TYPE_UW;
case BRW_REGISTER_TYPE_VF:
return BRW_REGISTER_TYPE_F;
case BRW_TYPE_B:
case BRW_TYPE_V:
return BRW_TYPE_W;
case BRW_TYPE_UB:
case BRW_TYPE_UV:
return BRW_TYPE_UW;
case BRW_TYPE_VF:
return BRW_TYPE_F;
default:
return type;
}
@ -315,13 +315,13 @@ brw_int_type(unsigned sz, bool is_signed)
{
switch (sz) {
case 1:
return (is_signed ? BRW_REGISTER_TYPE_B : BRW_REGISTER_TYPE_UB);
return (is_signed ? BRW_TYPE_B : BRW_TYPE_UB);
case 2:
return (is_signed ? BRW_REGISTER_TYPE_W : BRW_REGISTER_TYPE_UW);
return (is_signed ? BRW_TYPE_W : BRW_TYPE_UW);
case 4:
return (is_signed ? BRW_REGISTER_TYPE_D : BRW_REGISTER_TYPE_UD);
return (is_signed ? BRW_TYPE_D : BRW_TYPE_UD);
case 8:
return (is_signed ? BRW_REGISTER_TYPE_Q : BRW_REGISTER_TYPE_UQ);
return (is_signed ? BRW_TYPE_Q : BRW_TYPE_UQ);
default:
unreachable("Not reached.");
}
@ -334,7 +334,7 @@ brw_int_type(unsigned sz, bool is_signed)
* \param subnr register sub number
* \param negate register negate modifier
* \param abs register abs modifier
* \param type one of BRW_REGISTER_TYPE_x
* \param type one of BRW_TYPE_x
* \param vstride one of BRW_VERTICAL_STRIDE_x
* \param width one of BRW_WIDTH_x
* \param hstride one of BRW_HORIZONTAL_STRIDE_x
@ -394,7 +394,7 @@ brw_vec16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
subnr,
0,
0,
BRW_REGISTER_TYPE_F,
BRW_TYPE_F,
BRW_VERTICAL_STRIDE_16,
BRW_WIDTH_16,
BRW_HORIZONTAL_STRIDE_1,
@ -411,7 +411,7 @@ brw_vec8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
subnr,
0,
0,
BRW_REGISTER_TYPE_F,
BRW_TYPE_F,
BRW_VERTICAL_STRIDE_8,
BRW_WIDTH_8,
BRW_HORIZONTAL_STRIDE_1,
@ -428,7 +428,7 @@ brw_vec4_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
subnr,
0,
0,
BRW_REGISTER_TYPE_F,
BRW_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_1,
@ -445,7 +445,7 @@ brw_vec2_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
subnr,
0,
0,
BRW_REGISTER_TYPE_F,
BRW_TYPE_F,
BRW_VERTICAL_STRIDE_2,
BRW_WIDTH_2,
BRW_HORIZONTAL_STRIDE_1,
@ -462,7 +462,7 @@ brw_vec1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
subnr,
0,
0,
BRW_REGISTER_TYPE_F,
BRW_TYPE_F,
BRW_VERTICAL_STRIDE_0,
BRW_WIDTH_1,
BRW_HORIZONTAL_STRIDE_0,
@ -538,33 +538,33 @@ suboffset(struct brw_reg reg, unsigned delta)
static inline struct brw_reg
brw_uw16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
{
return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_TYPE_UW), subnr);
}
/** Construct unsigned word[8] register */
static inline struct brw_reg
brw_uw8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
{
return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_TYPE_UW), subnr);
}
/** Construct unsigned word[1] register */
static inline struct brw_reg
brw_uw1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
{
return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_TYPE_UW), subnr);
}
static inline struct brw_reg
brw_ud8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
{
return retype(brw_vec8_reg(file, nr, subnr), BRW_REGISTER_TYPE_UD);
return retype(brw_vec8_reg(file, nr, subnr), BRW_TYPE_UD);
}
static inline struct brw_reg
brw_ud1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
{
return retype(brw_vec1_reg(file, nr, subnr), BRW_REGISTER_TYPE_UD);
return retype(brw_vec1_reg(file, nr, subnr), BRW_TYPE_UD);
}
static inline struct brw_reg
@ -587,7 +587,7 @@ brw_imm_reg(enum brw_reg_type type)
static inline struct brw_reg
brw_imm_df(double df)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_DF);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_DF);
imm.df = df;
return imm;
}
@ -595,7 +595,7 @@ brw_imm_df(double df)
static inline struct brw_reg
brw_imm_u64(uint64_t u64)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_UQ);
imm.u64 = u64;
return imm;
}
@ -603,7 +603,7 @@ brw_imm_u64(uint64_t u64)
static inline struct brw_reg
brw_imm_f(float f)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_F);
imm.f = f;
return imm;
}
@ -612,7 +612,7 @@ brw_imm_f(float f)
static inline struct brw_reg
brw_imm_q(int64_t q)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_Q);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_Q);
imm.d64 = q;
return imm;
}
@ -621,7 +621,7 @@ brw_imm_q(int64_t q)
static inline struct brw_reg
brw_imm_uq(uint64_t uq)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_UQ);
imm.u64 = uq;
return imm;
}
@ -630,7 +630,7 @@ brw_imm_uq(uint64_t uq)
static inline struct brw_reg
brw_imm_d(int d)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_D);
imm.d = d;
return imm;
}
@ -639,7 +639,7 @@ brw_imm_d(int d)
static inline struct brw_reg
brw_imm_ud(unsigned ud)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_UD);
imm.ud = ud;
return imm;
}
@ -648,7 +648,7 @@ brw_imm_ud(unsigned ud)
static inline struct brw_reg
brw_imm_uw(uint16_t uw)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_UW);
imm.ud = uw | (uw << 16);
return imm;
}
@ -657,7 +657,7 @@ brw_imm_uw(uint16_t uw)
static inline struct brw_reg
brw_imm_w(int16_t w)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_W);
imm.ud = (uint16_t)w | (uint32_t)(uint16_t)w << 16;
return imm;
}
@ -670,7 +670,7 @@ brw_imm_w(int16_t w)
static inline struct brw_reg
brw_imm_v(unsigned v)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_V);
imm.ud = v;
return imm;
}
@ -679,7 +679,7 @@ brw_imm_v(unsigned v)
static inline struct brw_reg
brw_imm_uv(unsigned uv)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UV);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_UV);
imm.ud = uv;
return imm;
}
@ -688,7 +688,7 @@ brw_imm_uv(unsigned uv)
static inline struct brw_reg
brw_imm_vf(unsigned v)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_VF);
imm.ud = v;
return imm;
}
@ -696,7 +696,7 @@ brw_imm_vf(unsigned v)
static inline struct brw_reg
brw_imm_vf4(unsigned v0, unsigned v1, unsigned v2, unsigned v3)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
struct brw_reg imm = brw_imm_reg(BRW_TYPE_VF);
imm.vstride = BRW_VERTICAL_STRIDE_0;
imm.width = BRW_WIDTH_4;
imm.hstride = BRW_HORIZONTAL_STRIDE_1;
@ -856,7 +856,7 @@ brw_ip_reg(void)
0,
0,
0,
BRW_REGISTER_TYPE_UD,
BRW_TYPE_UD,
BRW_VERTICAL_STRIDE_4, /* ? */
BRW_WIDTH_1,
BRW_HORIZONTAL_STRIDE_0,
@ -872,7 +872,7 @@ brw_notification_reg(void)
0,
0,
0,
BRW_REGISTER_TYPE_UD,
BRW_TYPE_UD,
BRW_VERTICAL_STRIDE_0,
BRW_WIDTH_1,
BRW_HORIZONTAL_STRIDE_0,
@ -941,7 +941,7 @@ brw_mask_stack_reg(unsigned subnr)
{
return suboffset(retype(brw_vec16_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_MASK_STACK, 0),
BRW_REGISTER_TYPE_UB), subnr);
BRW_TYPE_UB), subnr);
}
static inline struct brw_reg
@ -1061,13 +1061,13 @@ get_element(struct brw_reg reg, unsigned elt)
static inline struct brw_reg
get_element_ud(struct brw_reg reg, unsigned elt)
{
return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
return vec1(suboffset(retype(reg, BRW_TYPE_UD), elt));
}
static inline struct brw_reg
get_element_d(struct brw_reg reg, unsigned elt)
{
return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_D), elt));
return vec1(suboffset(retype(reg, BRW_TYPE_D), elt));
}
static inline struct brw_reg
@ -1173,25 +1173,25 @@ deref_1f(struct brw_indirect ptr, int offset)
static inline struct brw_reg
deref_4b(struct brw_indirect ptr, int offset)
{
return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
return retype(deref_4f(ptr, offset), BRW_TYPE_B);
}
static inline struct brw_reg
deref_1uw(struct brw_indirect ptr, int offset)
{
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
return retype(deref_1f(ptr, offset), BRW_TYPE_UW);
}
static inline struct brw_reg
deref_1d(struct brw_indirect ptr, int offset)
{
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);
return retype(deref_1f(ptr, offset), BRW_TYPE_D);
}
static inline struct brw_reg
deref_1ud(struct brw_indirect ptr, int offset)
{
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
return retype(deref_1f(ptr, offset), BRW_TYPE_UD);
}
static inline struct brw_reg

2
src/intel/compiler/brw_reg_type.c
View file

@ -293,7 +293,7 @@ brw_reg_type_to_size(enum brw_reg_type type)
}
/**
* Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
* Converts a BRW_TYPE_* enum to a short string (F, UD, and so on).
*
* This is different than reg_encoding from brw_disasm.c in that it operates
* on the abstract enum values, rather than the generation-specific encoding.

18
src/intel/compiler/brw_reg_type.h
View file

@ -90,24 +90,6 @@ enum PACKED brw_reg_type {
BRW_TYPE_INVALID = 0b11111,
BRW_TYPE_LAST = BRW_TYPE_INVALID,
/** Backwards compatible long names: @{ */
BRW_REGISTER_TYPE_B = BRW_TYPE_B,
BRW_REGISTER_TYPE_W = BRW_TYPE_W,
BRW_REGISTER_TYPE_D = BRW_TYPE_D,
BRW_REGISTER_TYPE_Q = BRW_TYPE_Q,
BRW_REGISTER_TYPE_V = BRW_TYPE_V,
BRW_REGISTER_TYPE_UB = BRW_TYPE_UB,
BRW_REGISTER_TYPE_UW = BRW_TYPE_UW,
BRW_REGISTER_TYPE_UD = BRW_TYPE_UD,
BRW_REGISTER_TYPE_UQ = BRW_TYPE_UQ,
BRW_REGISTER_TYPE_UV = BRW_TYPE_UV,
BRW_REGISTER_TYPE_HF = BRW_TYPE_HF,
BRW_REGISTER_TYPE_F = BRW_TYPE_F,
BRW_REGISTER_TYPE_DF = BRW_TYPE_DF,
BRW_REGISTER_TYPE_VF = BRW_TYPE_VF,
BRW_REGISTER_TYPE_LAST = BRW_TYPE_INVALID,
/** *} */
};
static inline bool

132
src/intel/compiler/brw_shader.cpp
View file

@ -51,28 +51,28 @@ fs_reg_saturate_immediate(fs_reg *reg)
imm.df = reg->df;
switch (reg->type) {
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_UD:
case BRW_TYPE_D:
case BRW_TYPE_UW:
case BRW_TYPE_W:
case BRW_TYPE_UQ:
case BRW_TYPE_Q:
/* Nothing to do. */
return false;
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
sat_imm.f = SATURATE(imm.f);
break;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
sat_imm.df = SATURATE(imm.df);
break;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case BRW_TYPE_UB:
case BRW_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_V:
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_VF:
case BRW_TYPE_V:
case BRW_TYPE_UV:
case BRW_TYPE_VF:
unreachable("unimplemented: saturate vector immediate");
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
unreachable("unimplemented: saturate HF immediate");
default:
unreachable("invalid type");
@ -96,36 +96,36 @@ bool
fs_reg_negate_immediate(fs_reg *reg)
{
switch (reg->type) {
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_D:
case BRW_TYPE_UD:
reg->d = -reg->d;
return true;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW: {
case BRW_TYPE_W:
case BRW_TYPE_UW: {
uint16_t value = -(int16_t)reg->ud;
reg->ud = value | (uint32_t)value << 16;
return true;
}
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
reg->f = -reg->f;
return true;
case BRW_REGISTER_TYPE_VF:
case BRW_TYPE_VF:
reg->ud ^= 0x80808080;
return true;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
reg->df = -reg->df;
return true;
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_UQ:
case BRW_TYPE_Q:
reg->d64 = -reg->d64;
return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case BRW_TYPE_UB:
case BRW_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_V:
case BRW_TYPE_UV:
case BRW_TYPE_V:
assert(!"unimplemented: negate UV/V immediate");
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
reg->ud ^= 0x80008000;
return true;
default:
@ -139,40 +139,40 @@ bool
fs_reg_abs_immediate(fs_reg *reg)
{
switch (reg->type) {
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
reg->d = abs(reg->d);
return true;
case BRW_REGISTER_TYPE_W: {
case BRW_TYPE_W: {
uint16_t value = abs((int16_t)reg->ud);
reg->ud = value | (uint32_t)value << 16;
return true;
}
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
reg->f = fabsf(reg->f);
return true;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
reg->df = fabs(reg->df);
return true;
case BRW_REGISTER_TYPE_VF:
case BRW_TYPE_VF:
reg->ud &= ~0x80808080;
return true;
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_Q:
reg->d64 = imaxabs(reg->d64);
return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case BRW_TYPE_UB:
case BRW_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_UV:
case BRW_TYPE_UQ:
case BRW_TYPE_UD:
case BRW_TYPE_UW:
case BRW_TYPE_UV:
/* Presumably the absolute value modifier on an unsigned source is a
* nop, but it would be nice to confirm.
*/
assert(!"unimplemented: abs unsigned immediate");
case BRW_REGISTER_TYPE_V:
case BRW_TYPE_V:
assert(!"unimplemented: abs V immediate");
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
reg->ud &= ~0x80008000;
return true;
default:
@ -191,22 +191,22 @@ fs_reg::is_zero() const
assert(type_sz(type) > 1);
switch (type) {
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
assert((d & 0xffff) == ((d >> 16) & 0xffff));
return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
return f == 0;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
return df == 0;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_W:
case BRW_TYPE_UW:
assert((d & 0xffff) == ((d >> 16) & 0xffff));
return (d & 0xffff) == 0;
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_D:
case BRW_TYPE_UD:
return d == 0;
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_UQ:
case BRW_TYPE_Q:
return u64 == 0;
default:
return false;
@ -222,22 +222,22 @@ fs_reg::is_one() const
assert(type_sz(type) > 1);
switch (type) {
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
assert((d & 0xffff) == ((d >> 16) & 0xffff));
return (d & 0xffff) == 0x3c00;
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
return f == 1.0f;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
return df == 1.0;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_TYPE_W:
case BRW_TYPE_UW:
assert((d & 0xffff) == ((d >> 16) & 0xffff));
return (d & 0xffff) == 1;
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
case BRW_TYPE_D:
case BRW_TYPE_UD:
return d == 1;
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_UQ:
case BRW_TYPE_Q:
return u64 == 1;
default:
return false;
@ -253,19 +253,19 @@ fs_reg::is_negative_one() const
assert(type_sz(type) > 1);
switch (type) {
case BRW_REGISTER_TYPE_HF:
case BRW_TYPE_HF:
assert((d & 0xffff) == ((d >> 16) & 0xffff));
return (d & 0xffff) == 0xbc00;
case BRW_REGISTER_TYPE_F:
case BRW_TYPE_F:
return f == -1.0;
case BRW_REGISTER_TYPE_DF:
case BRW_TYPE_DF:
return df == -1.0;
case BRW_REGISTER_TYPE_W:
case BRW_TYPE_W:
assert((d & 0xffff) == ((d >> 16) & 0xffff));
return (d & 0xffff) == 0xffff;
case BRW_REGISTER_TYPE_D:
case BRW_TYPE_D:
return d == -1;
case BRW_REGISTER_TYPE_Q:
case BRW_TYPE_Q:
return d64 == -1;
default:
return false;

4
src/intel/compiler/test_eu_compact.cpp
View file

@ -237,8 +237,8 @@ TEST_P(Instructions, ADD_GRF_GRF_IMM)
TEST_P(Instructions, ADD_GRF_GRF_IMM_d)
{
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D);
struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D);
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_TYPE_D);
struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_TYPE_D);
brw_ADD(p, g0, g2, brw_imm_d(1));
}

598
src/intel/compiler/test_eu_validate.cpp
View file

File diff suppressed because it is too large Load diff

550
src/intel/compiler/test_fs_cmod_propagation.cpp
View file

File diff suppressed because it is too large Load diff

14
src/intel/compiler/test_fs_copy_propagation.cpp
View file

@ -119,10 +119,10 @@ copy_propagation(fs_visitor *v)
TEST_F(copy_propagation_test, basic)
{
fs_reg vgrf0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg vgrf1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg vgrf2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg vgrf3 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg vgrf0 = bld.vgrf(BRW_TYPE_F);
fs_reg vgrf1 = bld.vgrf(BRW_TYPE_F);
fs_reg vgrf2 = bld.vgrf(BRW_TYPE_F);
fs_reg vgrf3 = bld.vgrf(BRW_TYPE_F);
bld.MOV(vgrf0, vgrf2);
bld.ADD(vgrf1, vgrf0, vgrf3);
@ -160,9 +160,9 @@ TEST_F(copy_propagation_test, basic)
TEST_F(copy_propagation_test, maxmax_sat_imm)
{
fs_reg vgrf0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg vgrf1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg vgrf2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg vgrf0 = bld.vgrf(BRW_TYPE_F);
fs_reg vgrf1 = bld.vgrf(BRW_TYPE_F);
fs_reg vgrf2 = bld.vgrf(BRW_TYPE_F);
static const struct {
enum brw_conditional_mod conditional_mod;

164
src/intel/compiler/test_fs_saturate_propagation.cpp
View file

@ -120,10 +120,10 @@ saturate_propagation(fs_visitor *v)
TEST_F(saturate_propagation_test, basic)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.ADD(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
@ -154,11 +154,11 @@ TEST_F(saturate_propagation_test, basic)
TEST_F(saturate_propagation_test, other_non_saturated_use)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.ADD(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
bld.ADD(dst2, dst0, src0);
@ -191,10 +191,10 @@ TEST_F(saturate_propagation_test, other_non_saturated_use)
TEST_F(saturate_propagation_test, predicated_instruction)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.ADD(dst0, src0, src1)
->predicate = BRW_PREDICATE_NORMAL;
set_saturate(true, bld.MOV(dst1, dst0));
@ -225,9 +225,9 @@ TEST_F(saturate_propagation_test, predicated_instruction)
TEST_F(saturate_propagation_test, neg_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
bld.RNDU(dst0, src0);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@ -258,10 +258,10 @@ TEST_F(saturate_propagation_test, neg_mov_sat)
TEST_F(saturate_propagation_test, add_neg_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.ADD(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@ -295,9 +295,9 @@ TEST_F(saturate_propagation_test, add_neg_mov_sat)
TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = brw_imm_f(1.0f);
bld.ADD(dst0, src0, src1);
dst0.negate = true;
@ -332,10 +332,10 @@ TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat)
TEST_F(saturate_propagation_test, mul_neg_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.MUL(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@ -369,11 +369,11 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat)
TEST_F(saturate_propagation_test, mad_neg_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
fs_reg src2 = bld.vgrf(BRW_TYPE_F);
bld.MAD(dst0, src0, src1, src2);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@ -409,11 +409,11 @@ TEST_F(saturate_propagation_test, mad_neg_mov_sat)
TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = brw_imm_f(1.0f);
fs_reg src1 = brw_imm_f(-2.0f);
fs_reg src2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src2 = bld.vgrf(BRW_TYPE_F);
/* The builder for MAD tries to be helpful and not put immediates as direct
* sources. We want to test specifically that case.
*/
@ -453,11 +453,11 @@ TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat)
TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.MUL(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
dst0.negate = true;
@ -494,11 +494,11 @@ TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat)
TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.MUL(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@ -536,10 +536,10 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat)
TEST_F(saturate_propagation_test, abs_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.ADD(dst0, src0, src1);
dst0.abs = true;
set_saturate(true, bld.MOV(dst1, dst0));
@ -570,11 +570,11 @@ TEST_F(saturate_propagation_test, abs_mov_sat)
TEST_F(saturate_propagation_test, producer_saturates)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
set_saturate(true, bld.ADD(dst0, src0, src1));
set_saturate(true, bld.MOV(dst1, dst0));
bld.MOV(dst2, dst0);
@ -608,11 +608,11 @@ TEST_F(saturate_propagation_test, producer_saturates)
TEST_F(saturate_propagation_test, intervening_saturating_copy)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.ADD(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
set_saturate(true, bld.MOV(dst2, dst0));
@ -648,11 +648,11 @@ TEST_F(saturate_propagation_test, intervening_saturating_copy)
TEST_F(saturate_propagation_test, intervening_dest_write)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F, 4);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src2 = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F, 4);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
fs_reg src2 = bld.vgrf(BRW_TYPE_F, 2);
fs_reg tex_srcs[TEX_LOGICAL_NUM_SRCS];
tex_srcs[TEX_LOGICAL_SRC_COORDINATE] = src2;
@ -695,11 +695,11 @@ TEST_F(saturate_propagation_test, intervening_dest_write)
TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.MUL(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@ -737,10 +737,10 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
TEST_F(saturate_propagation_test, smaller_exec_size_consumer)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.ADD(dst0, src0, src1);
set_saturate(true, bld.group(8, 0).MOV(dst1, dst0));
@ -770,10 +770,10 @@ TEST_F(saturate_propagation_test, smaller_exec_size_consumer)
TEST_F(saturate_propagation_test, larger_exec_size_consumer)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.group(8, 0).ADD(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
@ -803,11 +803,11 @@ TEST_F(saturate_propagation_test, larger_exec_size_consumer)
TEST_F(saturate_propagation_test, offset_source_barrier)
{
fs_reg dst0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg dst0 = bld.vgrf(BRW_TYPE_F);
fs_reg dst1 = bld.vgrf(BRW_TYPE_F);
fs_reg dst2 = bld.vgrf(BRW_TYPE_F);
fs_reg src0 = bld.vgrf(BRW_TYPE_F);
fs_reg src1 = bld.vgrf(BRW_TYPE_F);
bld.group(16, 0).ADD(dst0, src0, src1);
bld.group(1, 0).ADD(dst1, component(dst0, 8), brw_imm_f(1.0f));
set_saturate(true, bld.group(16, 0).MOV(dst2, dst0));

104
src/intel/compiler/test_fs_scoreboard.cpp
View file

@ -150,10 +150,10 @@ TEST_F(scoreboard_test, RAW_inorder_inorder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg y = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
fs_reg y = bld.vgrf(BRW_TYPE_D);
bld.ADD( x, g[1], g[2]);
bld.MUL( y, g[3], g[4]);
bld.AND(g[5], x, y);
@ -176,9 +176,9 @@ TEST_F(scoreboard_test, RAW_inorder_outoforder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.ADD( x, g[1], g[2]);
bld.MUL( g[3], g[4], g[5]);
emit_SEND(bld, g[6], g[7], x);
@ -201,10 +201,10 @@ TEST_F(scoreboard_test, RAW_outoforder_inorder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg y = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
fs_reg y = bld.vgrf(BRW_TYPE_D);
emit_SEND(bld, x, g[1], g[2]);
bld.MUL( y, g[3], g[4]);
bld.AND( g[5], x, y);
@ -227,13 +227,13 @@ TEST_F(scoreboard_test, RAW_outoforder_outoforder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
/* The second SEND depends on the first, and would need to refer to two
* SBIDs. Since it is not possible we expect a SYNC instruction to be
* added.
*/
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
emit_SEND(bld, x, g[1], g[2]);
emit_SEND(bld, g[3], x, g[4])->sfid++;
@ -259,9 +259,9 @@ TEST_F(scoreboard_test, WAR_inorder_inorder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.ADD(g[1], x, g[2]);
bld.MUL(g[3], g[4], g[5]);
bld.AND( x, g[6], g[7]);
@ -284,9 +284,9 @@ TEST_F(scoreboard_test, WAR_inorder_outoforder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.ADD( g[1], x, g[2]);
bld.MUL( g[3], g[4], g[5]);
emit_SEND(bld, x, g[6], g[7]);
@ -309,9 +309,9 @@ TEST_F(scoreboard_test, WAR_outoforder_inorder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
emit_SEND(bld, g[1], g[2], x);
bld.MUL( g[4], g[5], g[6]);
bld.AND( x, g[7], g[8]);
@ -334,9 +334,9 @@ TEST_F(scoreboard_test, WAR_outoforder_outoforder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
emit_SEND(bld, g[1], g[2], x);
emit_SEND(bld, x, g[3], g[4])->sfid++;
@ -362,9 +362,9 @@ TEST_F(scoreboard_test, WAW_inorder_inorder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.ADD( x, g[1], g[2]);
bld.MUL(g[3], g[4], g[5]);
bld.AND( x, g[6], g[7]);
@ -392,9 +392,9 @@ TEST_F(scoreboard_test, WAW_inorder_outoforder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.ADD( x, g[1], g[2]);
bld.MUL( g[3], g[4], g[5]);
emit_SEND(bld, x, g[6], g[7]);
@ -417,9 +417,9 @@ TEST_F(scoreboard_test, WAW_outoforder_inorder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
emit_SEND(bld, x, g[1], g[2]);
bld.MUL( g[3], g[4], g[5]);
bld.AND( x, g[6], g[7]);
@ -442,9 +442,9 @@ TEST_F(scoreboard_test, WAW_outoforder_outoforder)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
emit_SEND(bld, x, g[1], g[2]);
emit_SEND(bld, x, g[3], g[4])->sfid++;
@ -471,9 +471,9 @@ TEST_F(scoreboard_test, loop1)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.emit(BRW_OPCODE_DO);
@ -501,9 +501,9 @@ TEST_F(scoreboard_test, loop2)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.XOR(g[3], g[1], g[2]);
bld.XOR(g[4], g[1], g[2]);
@ -536,9 +536,9 @@ TEST_F(scoreboard_test, loop3)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.emit(BRW_OPCODE_DO);
@ -573,9 +573,9 @@ TEST_F(scoreboard_test, conditional1)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.emit(BRW_OPCODE_IF);
@ -602,9 +602,9 @@ TEST_F(scoreboard_test, conditional2)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.XOR(g[3], g[1], g[2]);
bld.XOR(g[4], g[1], g[2]);
@ -634,9 +634,9 @@ TEST_F(scoreboard_test, conditional3)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.emit(BRW_OPCODE_IF);
@ -666,9 +666,9 @@ TEST_F(scoreboard_test, conditional4)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.emit(BRW_OPCODE_IF);
@ -698,9 +698,9 @@ TEST_F(scoreboard_test, conditional5)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.emit(BRW_OPCODE_IF);
@ -735,9 +735,9 @@ TEST_F(scoreboard_test, conditional6)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.emit(BRW_OPCODE_IF);
@ -779,9 +779,9 @@ TEST_F(scoreboard_test, conditional7)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.emit(BRW_OPCODE_IF);
@ -823,9 +823,9 @@ TEST_F(scoreboard_test, conditional8)
{
fs_reg g[16];
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
g[i] = bld.vgrf(BRW_REGISTER_TYPE_D);
g[i] = bld.vgrf(BRW_TYPE_D);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.XOR( x, g[1], g[2]);
bld.XOR(g[3], g[1], g[2]);
bld.XOR(g[4], g[1], g[2]);
@ -869,10 +869,10 @@ TEST_F(scoreboard_test, gfx125_RaR_over_different_pipes)
devinfo->verx10 = 125;
brw_init_isa_info(&compiler->isa, devinfo);
fs_reg a = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg b = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg f = bld.vgrf(BRW_REGISTER_TYPE_F);
fs_reg x = bld.vgrf(BRW_REGISTER_TYPE_D);
fs_reg a = bld.vgrf(BRW_TYPE_D);
fs_reg b = bld.vgrf(BRW_TYPE_D);
fs_reg f = bld.vgrf(BRW_TYPE_F);
fs_reg x = bld.vgrf(BRW_TYPE_D);
bld.ADD(f, x, x);
bld.ADD(a, x, x);