diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index 8560ef39a75..d3a07fe9c13 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -1040,13 +1040,14 @@ lower_load_constant(nir_builder *b, nir_intrinsic_instr *intrin, unsigned max_offset = b->shader->constant_data_size - load_size; offset = nir_umin(b, offset, nir_imm_int(b, max_offset)); - nir_ssa_def *const_data_base_addr = nir_pack_64_2x32_split(b, - nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW), - nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH)); + nir_ssa_def *const_data_addr = nir_pack_64_2x32_split(b, + nir_iadd(b, + nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW), + offset), + nir_imm_int(b, INSTRUCTION_STATE_POOL_MIN_ADDRESS >> 32)); nir_ssa_def *data = - nir_load_global_constant(b, nir_iadd(b, const_data_base_addr, - nir_u2u64(b, offset)), + nir_load_global_constant(b, const_data_addr, load_align, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size); diff --git a/src/intel/vulkan/anv_pipeline_cache.c b/src/intel/vulkan/anv_pipeline_cache.c index d50a84e2a58..6f00095ce59 100644 --- a/src/intel/vulkan/anv_pipeline_cache.c +++ b/src/intel/vulkan/anv_pipeline_cache.c @@ -123,10 +123,7 @@ anv_shader_bin_create(struct anv_device *device, .id = BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW, .value = shader_data_addr, }; - reloc_values[rv_count++] = (struct brw_shader_reloc_value) { - .id = BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH, - .value = shader_data_addr >> 32, - }; + assert(shader_data_addr >> 32 == INSTRUCTION_STATE_POOL_MIN_ADDRESS >> 32); reloc_values[rv_count++] = (struct brw_shader_reloc_value) { .id = BRW_SHADER_RELOC_SHADER_START_OFFSET, .value = shader->kernel.offset,