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broadcom/compiler: don't over-estimate latency of TMU instructions
Over-estimating latency can cause us to delay the critical paths of the shader unnecessarily, producing larger QPU programs that take more time to execute as a result (and it also adds register pressure) so striking a balance is important. The thread switching model in V3D is quite effective at hiding latency and usuallly we just need to hint it to delay TMU instructions a little bit to find the best compromise for performance. The new latency numbers have been chosen empirically by testing V3DV with Sponza and a few UE4 samples. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17451>
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1 changed files with 10 additions and 3 deletions
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@ -1146,6 +1146,13 @@ v3d_instr_delay_cb(nir_instr *instr, void *data)
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case nir_instr_type_phi:
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return 1;
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/* We should not use very large delays for TMU instructions. Typically,
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* thread switches will be sufficient to hide all or most of the latency,
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* so we typically only need a little bit of extra room. If we over-estimate
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* the latency here we may end up unnecesarily delaying the critical path in
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* the shader, which would have a negative effect in performance, so here
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* we are trying to strike a balance based on empirical testing.
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*/
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case nir_instr_type_intrinsic: {
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if (!c->disable_general_tmu_sched) {
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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@ -1154,10 +1161,10 @@ v3d_instr_delay_cb(nir_instr *instr, void *data)
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case nir_intrinsic_load_scratch:
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case nir_intrinsic_load_shared:
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case nir_intrinsic_image_load:
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return 30;
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return 3;
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case nir_intrinsic_load_ubo:
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if (nir_src_is_divergent(intr->src[1]))
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return 30;
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return 3;
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FALLTHROUGH;
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default:
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return 1;
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@ -1169,7 +1176,7 @@ v3d_instr_delay_cb(nir_instr *instr, void *data)
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}
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case nir_instr_type_tex:
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return 50;
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return 5;
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}
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return 0;
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