From 86f8b8860e4a2a95834a7cd514084b53880b17af Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue, 22 Oct 2024 23:07:44 -0700
Subject: [PATCH] brw: Use a smaller type for masked sub-32-bit shift values

Cuts 0.14% of instructions on Alchemist in affected fossil-db shaders
(all of which are in parallel-rdp).

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31833>
---
 src/intel/compiler/brw_from_nir.cpp | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp
index 3beaaa93ae1..be666f63a6b 100644
--- a/src/intel/compiler/brw_from_nir.cpp
+++ b/src/intel/compiler/brw_from_nir.cpp
@@ -1700,9 +1700,9 @@ brw_from_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
     */
    case nir_op_ishl:
       if (instr->def.bit_size < 32) {
-         bld.SHL(result,
-                 op[0],
-                 bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1)));
+         bld.SHL(result, op[0],
+                 bld.AND(subscript(op[1], BRW_TYPE_UW, 0),
+                         brw_imm_uw(instr->def.bit_size - 1)));
       } else {
          bld.SHL(result, op[0], op[1]);
       }
@@ -1710,9 +1710,9 @@ brw_from_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
       break;
    case nir_op_ishr:
       if (instr->def.bit_size < 32) {
-         bld.ASR(result,
-                 op[0],
-                 bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1)));
+         bld.ASR(result, op[0],
+                 bld.AND(subscript(op[1], BRW_TYPE_UW, 0),
+                         brw_imm_uw(instr->def.bit_size - 1)));
       } else {
          bld.ASR(result, op[0], op[1]);
       }
@@ -1720,9 +1720,9 @@ brw_from_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
       break;
    case nir_op_ushr:
       if (instr->def.bit_size < 32) {
-         bld.SHR(result,
-                 op[0],
-                 bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1)));
+         bld.SHR(result, op[0],
+                 bld.AND(subscript(op[1], BRW_TYPE_UW, 0),
+                         brw_imm_uw(instr->def.bit_size - 1)));
       } else {
          bld.SHR(result, op[0], op[1]);
       }