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radv: fix clearing DCC-compressed e5b9g9r9 images

Browse source 
Fixes
dEQP-VK.api.image_clearing.core.clear_color_image.2d.optimal.single_layer.e5b9g9r9_ufloat_pack32_33x128
with RADV_DEBUG=forcecompress on GFX10.3.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 21.1 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10176>
This commit is contained in:
Rhys Perry 2021-04-09 16:14:50 +01:00
parent 7ae2ba5da9
commit 86d903e88d
3 changed files with 30 additions and 6 deletions
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2
src/amd/vulkan/radv_formats.c
View file

@ -501,7 +501,7 @@ radv_is_atomic_format_supported(VkFormat format)
format == VK_FORMAT_R64_SINT;
}
static bool
bool
radv_is_storage_image_format_supported(struct radv_physical_device *physical_device,
VkFormat format)
{

32
src/amd/vulkan/radv_meta_clear.c
View file

@ -2014,11 +2014,23 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
else
internal_clear_value.depthStencil = clear_value->depthStencil;
bool disable_compression = false;
if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
uint32_t value;
format = VK_FORMAT_R32_UINT;
value = float3_to_rgb9e5(clear_value->color.float32);
internal_clear_value.color.uint32[0] = value;
bool blendable;
if (cs ? !radv_is_storage_image_format_supported(cmd_buffer->device->physical_device, format)
: !radv_is_colorbuffer_format_supported(cmd_buffer->device->physical_device, format,
&blendable)) {
format = VK_FORMAT_R32_UINT;
internal_clear_value.color.uint32[0] = float3_to_rgb9e5(clear_value->color.float32);
uint32_t queue_mask = radv_image_queue_family_mask(image, cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
/* Don't use compressed image stores because they will use an incompatible format. */
if (radv_layout_dcc_compressed(cmd_buffer->device, image, image_layout, false, queue_mask))
disable_compression = cs;
}
}
if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
@ -2053,15 +2065,25 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
surf.level = range->baseMipLevel + l;
surf.layer = range->baseArrayLayer + s;
surf.aspect_mask = range->aspectMask;
surf.disable_compression = false;
surf.disable_compression = disable_compression;
radv_meta_clear_image_cs(cmd_buffer, &surf, &internal_clear_value.color);
} else {
assert(!disable_compression);
radv_clear_image_layer(cmd_buffer, image, image_layout, range, format, l, s,
&internal_clear_value);
}
}
}
}
if (disable_compression) {
enum radv_cmd_flush_bits flush_bits = 0;
for (unsigned i = 0; i < range_count; i++) {
if (radv_dcc_enabled(image, ranges[i].baseMipLevel))
flush_bits |= radv_clear_dcc(cmd_buffer, image, &ranges[i], 0xffffffffu);
}
cmd_buffer->state.flush_bits |= flush_bits;
}
}
void

2
src/amd/vulkan/radv_private.h
View file

@ -1794,6 +1794,8 @@ uint32_t radv_translate_tex_numformat(VkFormat format, const struct util_format_
int first_non_void);
bool radv_format_pack_clear_color(VkFormat format, uint32_t clear_vals[2],
VkClearColorValue *value);
bool radv_is_storage_image_format_supported(struct radv_physical_device *physical_device,
VkFormat format);
bool radv_is_colorbuffer_format_supported(const struct radv_physical_device *pdevice,
VkFormat format, bool *blendable);
bool radv_dcc_formats_compatible(VkFormat format1, VkFormat format2);