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asahi: rm compact image atomic descriptors

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these cause robustness problems -- since the target type might not match the
shader for invalid apps -- and are a dubious microoptimization. can revisit
later. for now, fixes imageAtomic*/target mismatch test.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26614>
This commit is contained in:
Alyssa Rosenzweig 2023-11-20 10:48:09 -04:00
parent b13e3adb04
commit 86c4a72767
2 changed files with 8 additions and 22 deletions
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10
src/asahi/compiler/agx_nir_lower_texture.c
View file

@ -379,13 +379,11 @@ image_texel_address(nir_builder *b, nir_intrinsic_instr *intr,
(dim == GLSL_SAMPLER_DIM_CUBE) ||
(dim == GLSL_SAMPLER_DIM_3D);
/* The last 8 bytes of the 24-byte PBE descriptor contain either the
* software-defined atomic descriptor, or (if array image) a pointer to the
* descriptor. Grab the address.
/* The last 8 bytes of the 24-byte PBE descriptor points to the
* software-defined atomic descriptor. Grab the address.
*/
nir_def *meta_ptr = nir_iadd_imm(b, desc_address, 16);
if (layered)
meta_ptr = nir_load_global_constant(b, meta_ptr, 8, 1, 64);
nir_def *meta_meta_ptr = nir_iadd_imm(b, desc_address, 16);
nir_def *meta_ptr = nir_load_global_constant(b, meta_meta_ptr, 8, 1, 64);
if (dim == GLSL_SAMPLER_DIM_BUF && return_index) {
return nir_channel(b, coord, 0);

20
src/gallium/drivers/asahi/agx_state.c
View file

@ -1314,23 +1314,11 @@ agx_batch_upload_pbe(struct agx_batch *batch, struct agx_pbe_packed *out,
* 8 bytes as a sideband. We use it to provide metadata for image atomics.
*/
if (!cfg.extended) {
bool compact =
(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D ||
target == PIPE_TEXTURE_2D || target == PIPE_TEXTURE_RECT);
struct agx_ptr desc =
agx_pool_alloc_aligned(&batch->pool, AGX_ATOMIC_SOFTWARE_LENGTH, 8);
if (compact) {
struct agx_atomic_software_packed packed;
agx_pack_image_atomic_data(&packed, view);
STATIC_ASSERT(sizeof(cfg.software_defined) == 8);
memcpy(&cfg.software_defined, packed.opaque, 8);
} else {
struct agx_ptr desc = agx_pool_alloc_aligned(
&batch->pool, AGX_ATOMIC_SOFTWARE_LENGTH, 8);
agx_pack_image_atomic_data(desc.cpu, view);
cfg.software_defined = desc.gpu;
}
agx_pack_image_atomic_data(desc.cpu, view);
cfg.software_defined = desc.gpu;
}
};
}