intel/compiler/xe2: Handle 6-bit message type for Gfx20+

Message types are expanded to 6-bit encoding now. 5 bits are still the
same field from the Sampler Message Descriptor. The most significant bit
is now bit 31 of the Sampler Message Descriptor. The messages that have
'1 in bit 6 are only to support programmable offsets and those would
require message header. If a sampler type shows only 5 bits encoding, it
is implied bit 6 equal to 0 and there is no requirement for header.

v2 (idr): Trivial formatting changes.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27305>
This commit is contained in:
Sagar Ghuge 2023-03-04 18:23:06 -08:00 committed by Marge Bot
parent a9ed9cf88b
commit 8690a6b546

View file

@ -414,6 +414,20 @@ brw_sampler_desc(const struct intel_device_info *devinfo,
const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
SET_BITS(sampler, 11, 8));
/* From GFX20 Bspec: Shared Functions - Message Descriptor -
* Sampling Engine:
*
* Message Type[5] 31 This bit represents the upper bit of message type
* 6-bit encoding (c.f. [16:12]). This bit is set
* for messages with programmable offsets.
*/
if (devinfo->ver >= 20)
return desc | SET_BITS(msg_type & 0x1F, 16, 12) |
SET_BITS(simd_mode & 0x3, 18, 17) |
SET_BITS(simd_mode >> 2, 29, 29) |
SET_BITS(return_format, 30, 30) |
SET_BITS(msg_type >> 5, 31, 31);
/* From the CHV Bspec: Shared Functions - Message Descriptor -
* Sampling Engine:
*
@ -456,7 +470,9 @@ brw_sampler_desc_sampler(UNUSED const struct intel_device_info *devinfo,
static inline unsigned
brw_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc)
{
if (devinfo->ver >= 7)
if (devinfo->ver >= 20)
return GET_BITS(desc, 31, 31) << 5 | GET_BITS(desc, 16, 12);
else if (devinfo->ver >= 7)
return GET_BITS(desc, 16, 12);
else if (devinfo->verx10 >= 45)
return GET_BITS(desc, 15, 12);