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anv: Deduplicate render pass code
This lets us share the renderpass code and depth/stencil state code between gen 7 and gen 8.
This commit is contained in:
Kristian Høgsberg Kristensen
parent
ac4fd0ed21
commit
85f67cf16e
3 changed files with 179 additions and 343 deletions
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@ -556,176 +556,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.dirty = 0;
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}
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static void
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cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
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const struct anv_image_view *iview =
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anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
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const struct anv_image *image = iview ? iview->image : NULL;
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const struct anv_format *anv_format =
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iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
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const bool has_depth = iview && anv_format->has_depth;
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const bool has_stencil = iview && anv_format->has_stencil;
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/* Emit 3DSTATE_DEPTH_BUFFER */
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if (has_depth) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
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.SurfaceType = SURFTYPE_2D,
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.DepthWriteEnable = true,
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.StencilWriteEnable = has_stencil,
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.HierarchicalDepthBufferEnable = false,
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.SurfaceFormat = isl_surf_get_depth_format(&device->isl_dev,
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&image->depth_surface.isl),
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.SurfacePitch = image->depth_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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.offset = image->depth_surface.offset,
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},
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.Height = fb->height - 1,
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.Width = fb->width - 1,
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.LOD = 0,
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.Depth = 1 - 1,
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.MinimumArrayElement = 0,
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.DepthBufferObjectControlState = GENX(MOCS),
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.RenderTargetViewExtent = 1 - 1);
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} else {
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/* Even when no depth buffer is present, the hardware requires that
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* 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
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*
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* If a null depth buffer is bound, the driver must instead bind depth as:
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* 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
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* 3DSTATE_DEPTH.Width = 1
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* 3DSTATE_DEPTH.Height = 1
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* 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
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* 3DSTATE_DEPTH.SurfaceBaseAddress = 0
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* 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
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* 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
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* 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
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*
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* The PRM is wrong, though. The width and height must be programmed to
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* actual framebuffer's width and height, even when neither depth buffer
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* nor stencil buffer is present.
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*/
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
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.SurfaceType = SURFTYPE_2D,
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.SurfaceFormat = D16_UNORM,
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.Width = fb->width - 1,
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.Height = fb->height - 1,
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.StencilWriteEnable = has_stencil);
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}
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/* Emit 3DSTATE_STENCIL_BUFFER */
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if (has_stencil) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
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# if (ANV_IS_HASWELL)
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.StencilBufferEnable = true,
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# endif
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.StencilBufferObjectControlState = GENX(MOCS),
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/* Stencil buffers have strange pitch. The PRM says:
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*
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* The pitch must be set to 2x the value computed based on width,
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* as the stencil buffer is stored with two rows interleaved.
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*/
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.SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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.offset = image->offset + image->stencil_surface.offset,
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});
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} else {
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_STENCIL_BUFFER);
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}
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/* Disable hierarchial depth buffers. */
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_HIER_DEPTH_BUFFER);
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/* Clear the clear params. */
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CLEAR_PARAMS);
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}
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/**
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* @see anv_cmd_buffer_set_subpass()
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*/
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GENX_FUNC(GEN7, GEN7) void
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genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
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struct anv_subpass *subpass)
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{
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cmd_buffer->state.subpass = subpass;
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cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
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cmd_buffer_emit_depth_stencil(cmd_buffer);
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}
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void genX(CmdBeginRenderPass)(
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VkCommandBuffer commandBuffer,
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const VkRenderPassBeginInfo* pRenderPassBegin,
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VkSubpassContents contents)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
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ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
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cmd_buffer->state.framebuffer = framebuffer;
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cmd_buffer->state.pass = pass;
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anv_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
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genX(flush_pipeline_select_3d)(cmd_buffer);
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const VkRect2D *render_area = &pRenderPassBegin->renderArea;
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_DRAWING_RECTANGLE,
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.ClippedDrawingRectangleYMin = render_area->offset.y,
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.ClippedDrawingRectangleXMin = render_area->offset.x,
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.ClippedDrawingRectangleYMax =
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render_area->offset.y + render_area->extent.height - 1,
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.ClippedDrawingRectangleXMax =
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render_area->offset.x + render_area->extent.width - 1,
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.DrawingRectangleOriginY = 0,
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.DrawingRectangleOriginX = 0);
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gen7_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses);
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anv_cmd_buffer_clear_subpass(cmd_buffer);
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}
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void genX(CmdNextSubpass)(
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VkCommandBuffer commandBuffer,
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VkSubpassContents contents)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
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anv_cmd_buffer_resolve_subpass(cmd_buffer);
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gen7_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1);
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anv_cmd_buffer_clear_subpass(cmd_buffer);
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}
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void genX(CmdEndRenderPass)(
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VkCommandBuffer commandBuffer)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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anv_cmd_buffer_resolve_subpass(cmd_buffer);
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/* Emit a flushing pipe control at the end of a pass. This is kind of a
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* hack but it ensures that render targets always actually get written.
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* Eventually, we should do flushing based on image format transitions
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* or something of that nature.
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*/
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anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
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.PostSyncOperation = NoWrite,
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.RenderTargetCacheFlushEnable = true,
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.InstructionCacheInvalidateEnable = true,
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.DepthCacheFlushEnable = true,
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.VFCacheInvalidationEnable = true,
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.TextureCacheInvalidationEnable = true,
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.CommandStreamerStallEnable = true);
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}
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void genX(CmdSetEvent)(
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VkCommandBuffer commandBuffer,
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VkEvent event,
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@ -602,179 +602,6 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.compute_dirty = 0;
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}
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static void
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cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
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const struct anv_image_view *iview =
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anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
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const struct anv_image *image = iview ? iview->image : NULL;
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const struct anv_format *anv_format =
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iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
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const bool has_depth = iview && anv_format->has_depth;
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const bool has_stencil = iview && anv_format->has_stencil;
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/* FIXME: Implement the PMA stall W/A */
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/* FIXME: Width and Height are wrong */
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/* Emit 3DSTATE_DEPTH_BUFFER */
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if (has_depth) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
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.SurfaceType = SURFTYPE_2D,
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.DepthWriteEnable = true,
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.StencilWriteEnable = has_stencil,
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.HierarchicalDepthBufferEnable = false,
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.SurfaceFormat = isl_surf_get_depth_format(&device->isl_dev,
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&image->depth_surface.isl),
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.SurfacePitch = image->depth_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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.offset = image->depth_surface.offset,
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},
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.Height = fb->height - 1,
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.Width = fb->width - 1,
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.LOD = 0,
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.Depth = 1 - 1,
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.MinimumArrayElement = 0,
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.DepthBufferObjectControlState = GENX(MOCS),
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.RenderTargetViewExtent = 1 - 1,
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.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2);
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} else {
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/* Even when no depth buffer is present, the hardware requires that
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* 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
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*
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* If a null depth buffer is bound, the driver must instead bind depth as:
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* 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
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* 3DSTATE_DEPTH.Width = 1
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* 3DSTATE_DEPTH.Height = 1
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* 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
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* 3DSTATE_DEPTH.SurfaceBaseAddress = 0
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* 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
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* 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
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* 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
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*
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* The PRM is wrong, though. The width and height must be programmed to
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* actual framebuffer's width and height, even when neither depth buffer
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* nor stencil buffer is present.
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*/
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
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.SurfaceType = SURFTYPE_2D,
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.SurfaceFormat = D16_UNORM,
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.Width = fb->width - 1,
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.Height = fb->height - 1,
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.StencilWriteEnable = has_stencil);
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}
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/* Emit 3DSTATE_STENCIL_BUFFER */
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if (has_stencil) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
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.StencilBufferEnable = true,
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.StencilBufferObjectControlState = GENX(MOCS),
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/* Stencil buffers have strange pitch. The PRM says:
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*
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* The pitch must be set to 2x the value computed based on width,
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* as the stencil buffer is stored with two rows interleaved.
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*/
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.SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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.offset = image->offset + image->stencil_surface.offset,
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},
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.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2);
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} else {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER));
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}
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/* Disable hierarchial depth buffers. */
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER));
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/* Clear the clear params. */
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS));
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}
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/**
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* @see anv_cmd_buffer_set_subpass()
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*/
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void
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genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
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struct anv_subpass *subpass)
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{
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cmd_buffer->state.subpass = subpass;
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cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
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cmd_buffer_emit_depth_stencil(cmd_buffer);
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}
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void genX(CmdBeginRenderPass)(
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VkCommandBuffer commandBuffer,
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const VkRenderPassBeginInfo* pRenderPassBegin,
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VkSubpassContents contents)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
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ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
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cmd_buffer->state.framebuffer = framebuffer;
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cmd_buffer->state.pass = pass;
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anv_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
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genX(flush_pipeline_select_3d)(cmd_buffer);
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const VkRect2D *render_area = &pRenderPassBegin->renderArea;
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DRAWING_RECTANGLE),
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.ClippedDrawingRectangleYMin = render_area->offset.y,
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.ClippedDrawingRectangleXMin = render_area->offset.x,
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.ClippedDrawingRectangleYMax =
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render_area->offset.y + render_area->extent.height - 1,
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.ClippedDrawingRectangleXMax =
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render_area->offset.x + render_area->extent.width - 1,
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.DrawingRectangleOriginY = 0,
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.DrawingRectangleOriginX = 0);
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genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses);
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anv_cmd_buffer_clear_subpass(cmd_buffer);
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}
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void genX(CmdNextSubpass)(
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VkCommandBuffer commandBuffer,
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VkSubpassContents contents)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
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anv_cmd_buffer_resolve_subpass(cmd_buffer);
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genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
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anv_cmd_buffer_clear_subpass(cmd_buffer);
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}
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void genX(CmdEndRenderPass)(
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VkCommandBuffer commandBuffer)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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anv_cmd_buffer_resolve_subpass(cmd_buffer);
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/* Emit a flushing pipe control at the end of a pass. This is kind of a
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* hack but it ensures that render targets always actually get written.
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* Eventually, we should do flushing based on image format transitions
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* or something of that nature.
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*/
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
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.PostSyncOperation = NoWrite,
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.RenderTargetCacheFlushEnable = true,
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.InstructionCacheInvalidateEnable = true,
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.DepthCacheFlushEnable = true,
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.VFCacheInvalidationEnable = true,
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.TextureCacheInvalidationEnable = true,
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.CommandStreamerStallEnable = true);
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}
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static void
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emit_ps_depth_count(struct anv_batch *batch,
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struct anv_bo *bo, uint32_t offset)
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@ -548,3 +548,182 @@ genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.current_pipeline = _3D;
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}
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}
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static void
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cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
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const struct anv_image_view *iview =
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anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
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const struct anv_image *image = iview ? iview->image : NULL;
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const struct anv_format *anv_format =
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iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
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const bool has_depth = iview && anv_format->has_depth;
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const bool has_stencil = iview && anv_format->has_stencil;
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/* FIXME: Implement the PMA stall W/A */
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/* FIXME: Width and Height are wrong */
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/* Emit 3DSTATE_DEPTH_BUFFER */
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if (has_depth) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
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.SurfaceType = SURFTYPE_2D,
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.DepthWriteEnable = true,
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.StencilWriteEnable = has_stencil,
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.HierarchicalDepthBufferEnable = false,
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.SurfaceFormat = isl_surf_get_depth_format(&device->isl_dev,
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&image->depth_surface.isl),
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.SurfacePitch = image->depth_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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.offset = image->depth_surface.offset,
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},
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.Height = fb->height - 1,
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.Width = fb->width - 1,
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.LOD = 0,
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.Depth = 1 - 1,
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.MinimumArrayElement = 0,
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.DepthBufferObjectControlState = GENX(MOCS),
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#if ANV_GEN >= 8
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.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2,
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#endif
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.RenderTargetViewExtent = 1 - 1);
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} else {
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/* Even when no depth buffer is present, the hardware requires that
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* 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
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*
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* If a null depth buffer is bound, the driver must instead bind depth as:
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* 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
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* 3DSTATE_DEPTH.Width = 1
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* 3DSTATE_DEPTH.Height = 1
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* 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
|
||||
* 3DSTATE_DEPTH.SurfaceBaseAddress = 0
|
||||
* 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
|
||||
* 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
|
||||
* 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
|
||||
*
|
||||
* The PRM is wrong, though. The width and height must be programmed to
|
||||
* actual framebuffer's width and height, even when neither depth buffer
|
||||
* nor stencil buffer is present.
|
||||
*/
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
|
||||
.SurfaceType = SURFTYPE_2D,
|
||||
.SurfaceFormat = D16_UNORM,
|
||||
.Width = fb->width - 1,
|
||||
.Height = fb->height - 1,
|
||||
.StencilWriteEnable = has_stencil);
|
||||
}
|
||||
|
||||
/* Emit 3DSTATE_STENCIL_BUFFER */
|
||||
if (has_stencil) {
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
|
||||
#if ANV_GEN >= 8 || ANV_IS_HASWELL
|
||||
.StencilBufferEnable = true,
|
||||
#endif
|
||||
.StencilBufferObjectControlState = GENX(MOCS),
|
||||
|
||||
/* Stencil buffers have strange pitch. The PRM says:
|
||||
*
|
||||
* The pitch must be set to 2x the value computed based on width,
|
||||
* as the stencil buffer is stored with two rows interleaved.
|
||||
*/
|
||||
.SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
|
||||
|
||||
#if ANV_GEN >= 8
|
||||
.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2,
|
||||
#endif
|
||||
.SurfaceBaseAddress = {
|
||||
.bo = image->bo,
|
||||
.offset = image->offset + image->stencil_surface.offset,
|
||||
});
|
||||
} else {
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER));
|
||||
}
|
||||
|
||||
/* Disable hierarchial depth buffers. */
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER));
|
||||
|
||||
/* Clear the clear params. */
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @see anv_cmd_buffer_set_subpass()
|
||||
*/
|
||||
void
|
||||
genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
|
||||
struct anv_subpass *subpass)
|
||||
{
|
||||
cmd_buffer->state.subpass = subpass;
|
||||
|
||||
cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
|
||||
|
||||
cmd_buffer_emit_depth_stencil(cmd_buffer);
|
||||
}
|
||||
|
||||
void genX(CmdBeginRenderPass)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
const VkRenderPassBeginInfo* pRenderPassBegin,
|
||||
VkSubpassContents contents)
|
||||
{
|
||||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
|
||||
ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
|
||||
|
||||
cmd_buffer->state.framebuffer = framebuffer;
|
||||
cmd_buffer->state.pass = pass;
|
||||
anv_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
|
||||
|
||||
genX(flush_pipeline_select_3d)(cmd_buffer);
|
||||
|
||||
const VkRect2D *render_area = &pRenderPassBegin->renderArea;
|
||||
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DRAWING_RECTANGLE),
|
||||
.ClippedDrawingRectangleYMin = render_area->offset.y,
|
||||
.ClippedDrawingRectangleXMin = render_area->offset.x,
|
||||
.ClippedDrawingRectangleYMax =
|
||||
render_area->offset.y + render_area->extent.height - 1,
|
||||
.ClippedDrawingRectangleXMax =
|
||||
render_area->offset.x + render_area->extent.width - 1,
|
||||
.DrawingRectangleOriginY = 0,
|
||||
.DrawingRectangleOriginX = 0);
|
||||
|
||||
genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses);
|
||||
anv_cmd_buffer_clear_subpass(cmd_buffer);
|
||||
}
|
||||
|
||||
void genX(CmdNextSubpass)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
VkSubpassContents contents)
|
||||
{
|
||||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
|
||||
assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
|
||||
|
||||
anv_cmd_buffer_resolve_subpass(cmd_buffer);
|
||||
genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
|
||||
anv_cmd_buffer_clear_subpass(cmd_buffer);
|
||||
}
|
||||
|
||||
void genX(CmdEndRenderPass)(
|
||||
VkCommandBuffer commandBuffer)
|
||||
{
|
||||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
|
||||
anv_cmd_buffer_resolve_subpass(cmd_buffer);
|
||||
|
||||
/* Emit a flushing pipe control at the end of a pass. This is kind of a
|
||||
* hack but it ensures that render targets always actually get written.
|
||||
* Eventually, we should do flushing based on image format transitions
|
||||
* or something of that nature.
|
||||
*/
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
|
||||
.PostSyncOperation = NoWrite,
|
||||
.RenderTargetCacheFlushEnable = true,
|
||||
.InstructionCacheInvalidateEnable = true,
|
||||
.DepthCacheFlushEnable = true,
|
||||
.VFCacheInvalidationEnable = true,
|
||||
.TextureCacheInvalidationEnable = true,
|
||||
.CommandStreamerStallEnable = true);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue