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intel/brw: Remove Gfx8- code from scheduler
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
6e88fa8a77
commit
85eb672325
1 changed files with 6 additions and 96 deletions
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@ -64,8 +64,7 @@ struct schedule_node_child;
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class schedule_node : public exec_node
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{
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public:
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void set_latency_gfx4();
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void set_latency_gfx7(const struct brw_isa_info *isa);
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void set_latency(const struct brw_isa_info *isa);
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backend_instruction *inst;
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schedule_node_child *children;
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@ -149,48 +148,8 @@ exit_initial_unblocked_time(const schedule_node *n)
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}
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void
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schedule_node::set_latency_gfx4()
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schedule_node::set_latency(const struct brw_isa_info *isa)
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{
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int chans = 8;
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int math_latency = 22;
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switch (inst->opcode) {
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case SHADER_OPCODE_RCP:
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this->latency = 1 * chans * math_latency;
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break;
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case SHADER_OPCODE_RSQ:
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this->latency = 2 * chans * math_latency;
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break;
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case SHADER_OPCODE_INT_QUOTIENT:
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case SHADER_OPCODE_SQRT:
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case SHADER_OPCODE_LOG2:
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/* full precision log. partial is 2. */
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this->latency = 3 * chans * math_latency;
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break;
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case SHADER_OPCODE_INT_REMAINDER:
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case SHADER_OPCODE_EXP2:
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/* full precision. partial is 3, same throughput. */
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this->latency = 4 * chans * math_latency;
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break;
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case SHADER_OPCODE_POW:
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this->latency = 8 * chans * math_latency;
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break;
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case SHADER_OPCODE_SIN:
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case SHADER_OPCODE_COS:
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/* minimum latency, max is 12 rounds. */
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this->latency = 5 * chans * math_latency;
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break;
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default:
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this->latency = 2;
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break;
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}
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}
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void
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schedule_node::set_latency_gfx7(const struct brw_isa_info *isa)
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{
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const bool is_haswell = isa->devinfo->verx10 == 75;
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switch (inst->opcode) {
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case BRW_OPCODE_MAD:
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/* 2 cycles
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@ -215,7 +174,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa)
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/* Our register allocator doesn't know about register banks, so use the
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* higher latency.
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*/
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latency = is_haswell ? 16 : 18;
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latency = 18;
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break;
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case BRW_OPCODE_LRP:
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@ -260,7 +219,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa)
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*
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* Same for exp2, log2, rsq, sqrt, sin, cos.
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*/
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latency = is_haswell ? 14 : 16;
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latency = 16;
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break;
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case SHADER_OPCODE_POW:
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@ -271,7 +230,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa)
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* math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
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* mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
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*/
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latency = is_haswell ? 22 : 24;
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latency = 24;
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break;
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case SHADER_OPCODE_TEX:
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@ -431,13 +390,11 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa)
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case GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE:
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case GFX7_DATAPORT_RC_TYPED_SURFACE_READ:
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/* See also SHADER_OPCODE_TYPED_SURFACE_READ */
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assert(!is_haswell);
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latency = 600;
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break;
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case GFX7_DATAPORT_RC_TYPED_ATOMIC_OP:
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/* See also SHADER_OPCODE_TYPED_ATOMIC */
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assert(!is_haswell);
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latency = 14000;
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break;
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@ -493,7 +450,6 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa)
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* gives an average latency of 583 cycles per surface read,
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* standard deviation 0.9%.
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*/
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assert(!is_haswell);
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latency = 600;
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break;
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@ -512,7 +468,6 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa)
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* collisions between threads and favorable pipelining has been
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* seen to be reduced by a factor of 100.
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*/
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assert(!is_haswell);
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latency = 14000;
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break;
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@ -659,22 +614,16 @@ public:
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this->nodes_len = s->cfg->last_block()->end_ip + 1;
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this->nodes = linear_zalloc_array(lin_ctx, schedule_node, this->nodes_len);
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const struct intel_device_info *devinfo = bs->devinfo;
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const struct brw_isa_info *isa = &bs->compiler->isa;
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schedule_node *n = nodes;
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foreach_block_and_inst(block, backend_instruction, inst, s->cfg) {
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n->inst = inst;
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/* We can't measure Gfx6 timings directly but expect them to be much
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* closer to Gfx7 than Gfx4.
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*/
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if (!post_reg_alloc)
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n->latency = 1;
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else if (devinfo->ver >= 6)
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n->set_latency_gfx7(isa);
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else
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n->set_latency_gfx4();
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n->set_latency(isa);
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n++;
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}
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@ -1534,8 +1483,6 @@ fs_instruction_scheduler::choose_instruction_to_schedule()
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* latency.
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*/
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foreach_in_list(schedule_node, n, ¤t.available) {
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fs_inst *inst = (fs_inst *)n->inst;
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if (!chosen) {
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chosen = n;
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chosen_register_pressure_benefit =
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@ -1574,30 +1521,6 @@ fs_instruction_scheduler::choose_instruction_to_schedule()
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} else if (n->tmp.cand_generation < chosen->tmp.cand_generation) {
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continue;
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}
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/* On MRF-using chips, prefer non-SEND instructions. If we don't
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* do this, then because we prefer instructions that just became
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* candidates, we'll end up in a pattern of scheduling a SEND,
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* then the MRFs for the next SEND, then the next SEND, then the
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* MRFs, etc., without ever consuming the results of a send.
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*/
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if (v->devinfo->ver < 7) {
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fs_inst *chosen_inst = (fs_inst *)chosen->inst;
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/* We use size_written > 4 * exec_size as our test for the kind
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* of send instruction to avoid -- only sends generate many
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* regs, and a single-result send is probably actually reducing
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* register pressure.
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*/
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if (inst->size_written <= 4 * inst->exec_size &&
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chosen_inst->size_written > 4 * chosen_inst->exec_size) {
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chosen = n;
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chosen_register_pressure_benefit = register_pressure_benefit;
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continue;
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} else if (inst->size_written > chosen_inst->size_written) {
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continue;
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}
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}
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}
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/* For instructions pushed on the cands list at the same time, prefer
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@ -1704,19 +1627,6 @@ instruction_scheduler::update_children(schedule_node *chosen)
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}
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}
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current.cand_generation++;
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/* Shared resource: the mathbox. There's one mathbox per EU on Gfx6+
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* but it's more limited pre-gfx6, so if we send something off to it then
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* the next math instruction isn't going to make progress until the first
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* is done.
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*/
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if (bs->devinfo->ver < 6 && chosen->inst->is_math()) {
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foreach_in_list(schedule_node, n, ¤t.available) {
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if (n->inst->is_math())
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n->tmp.unblocked_time = MAX2(n->tmp.unblocked_time,
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current.time + chosen->latency);
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}
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}
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}
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void
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