From 85d7eb730a1cbfbd4c9b2ecd017f6b8dab40b20d Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 30 Sep 2014 01:15:55 -0700 Subject: [PATCH] i965: Add a BRW_MOCS_PTE #define. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Like BDW_MOCS_WB and BDW_MOCS_WT, this specifies that we want to use all three caches (L3, LLC, and eLLC where available), but leaves the LLC caching mode up to the kernel's page table entry. This allows the kernel to pick WB/WT/UC based on whether it's using a buffer for scanout. Signed-off-by: Kenneth Graunke Reviewed-by: Daniel Vetter Reviewed-by: Kristian Høgsberg Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit d489a8a73d273e9042b3de49085576c2acd5153a) --- src/mesa/drivers/dri/i965/brw_defines.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 968aba1fb22..9470fbc17e2 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -2312,9 +2312,13 @@ enum brw_wm_barycentric_interp_mode { #define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1) #define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1) -/* Broadwell: write-back or write-through; always use all the caches. */ -#define BDW_MOCS_WB 0x78 -#define BDW_MOCS_WT 0x58 +/* Broadwell: these defines always use all available caches (L3, LLC, eLLC), + * and let you force write-back (WB) or write-through (WT) caching, or leave + * it up to the page table entry (PTE) specified by the kernel. + */ +#define BDW_MOCS_WB 0x78 +#define BDW_MOCS_WT 0x58 +#define BDW_MOCS_PTE 0x18 #include "intel_chipset.h"