From 85a5d6233b1383ec4140896ca08c29bd85b75d99 Mon Sep 17 00:00:00 2001 From: Peyton Lee Date: Thu, 23 Apr 2026 08:09:47 +0000 Subject: [PATCH] amd/vpelib: add alpha fill support check Add helper functions check_alpha_fill_support() Also fix incorrect color format naming. Signed-off-by: Peyton Lee Part-of: --- src/amd/vpelib/inc/vpe_hw_types.h | 125 +++++++++--------- src/amd/vpelib/inc/vpe_types.h | 37 +++--- .../src/chip/vpe10/inc/vpe10_resource.h | 6 + .../vpelib/src/chip/vpe10/vpe10_background.c | 2 +- src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c | 3 +- .../vpelib/src/chip/vpe10/vpe10_resource.c | 109 +++++++-------- .../src/chip/vpe10/vpe10_vpe_desc_writer.c | 7 - .../vpelib/src/chip/vpe11/vpe11_resource.c | 14 +- .../src/chip/vpe11/vpe11_vpe_desc_writer.c | 3 - src/amd/vpelib/src/core/color.c | 1 + src/amd/vpelib/src/core/common.c | 10 +- src/amd/vpelib/src/core/config_writer.c | 16 +-- src/amd/vpelib/src/core/inc/config_writer.h | 9 +- src/amd/vpelib/src/core/inc/opp.h | 1 + src/amd/vpelib/src/core/inc/reg_helper.h | 21 +++ src/amd/vpelib/src/core/inc/resource.h | 10 ++ src/amd/vpelib/src/core/inc/vpe_command.h | 4 +- src/amd/vpelib/src/core/inc/vpe_desc_writer.h | 3 - src/amd/vpelib/src/core/inc/vpe_priv.h | 11 +- src/amd/vpelib/src/core/resource.c | 65 ++++++++- src/amd/vpelib/src/core/vpe_visual_confirm.c | 4 +- src/amd/vpelib/src/core/vpelib.c | 38 ++---- src/amd/vpelib/src/utils/conversion.c | 19 +++ src/amd/vpelib/src/utils/inc/conversion.h | 2 + 24 files changed, 297 insertions(+), 223 deletions(-) diff --git a/src/amd/vpelib/inc/vpe_hw_types.h b/src/amd/vpelib/inc/vpe_hw_types.h index 26fc7cfbffc..d34a8040dd3 100644 --- a/src/amd/vpelib/inc/vpe_hw_types.h +++ b/src/amd/vpelib/inc/vpe_hw_types.h @@ -222,70 +222,67 @@ struct vpe_plane_dcc_param { */ enum vpe_surface_pixel_format { VPE_SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, - /*16 bpp*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, - /*16 bpp*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565, - /*32 bpp*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, - /*32 bpp swaped*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, - /*32 bpp alpha rotated*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888, - /*32 bpp swaped & alpha rotated*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, - - VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, - /*swaped*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, - /*alpha rotated*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102, - /*swaped & alpha rotated*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102, - - /*64 bpp */ - VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, - /*float*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, - /*swaped & float*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, - /*alpha rotated*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F, - /*swaped & alpha rotated*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F, - - VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888, - /*swaped*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888, - /*rotated*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888, - /*swaped & rotated*/ - VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888, - /*grow graphics here if necessary */ - VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, - VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, - VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, - VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, - VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCrCb, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCbCr, - VPE_SURFACE_PIXEL_FORMAT_SUBSAMPLE_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCbCr, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888, - VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, //seems to be dummy, not part of surface pixel register values - VPE_SURFACE_PIXEL_FORMAT_VIDEO_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, - VPE_SURFACE_PIXEL_FORMAT_INVALID - - /*grow 444 video here if necessary */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, /**< RGB 16 bpp A1 R5 G5 B5 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565, /**< RGB 16 bpp no alpha R5 G6 B5 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, /**< RGB 32 bpp A8 R8 G8 B8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, /**< Swapped RGB 32 bpp A8 B8 G8 R8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888, /**< Alpha rotated RGB 32 bpp R8 G8 B8 A8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, /**< Swapped and alpha rotated RGB 32 bpp + B8 G8 R8 A8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, /**< RGB 32 bpp A2 R10 G10 B10 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, /**< Swapped RGB 32 bpp A2 B10 G10 R10 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102, /**< Alpha rotated RGB 32 bpp R10 G10 B10 A2*/ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102, /**< Swapped and alpha rotated RGB 32 bpp + A2 B10 G10 R10 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, /**< RGB 64 bpp A16 R16 G16 B16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, /**< Floating point RGB 64 bpp A16 R16 G16 B16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, /**< Floating point swapped RGB 64 bpp + A16 B16 G16 R16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F, /**< Floating point alpha rotated RGB 64 bpp + R16 G16 R16 A16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F, /**< Floating point swapped and alpha rotated + RGB 64 bpp B16 G16 R16 A16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888, /**< Opaque RGB 32 bpp X8 (ignored) R8 G8 B8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888, /**< Opaque swapped RGB 32 bpp X8 B8 G8 R8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888, /**< Opaque rotated RGB 32 bpp R8 G8 B8 X8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888, /**< Opaque rotated and swapped RGB 32 bpp + B8 G8 R8 X8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, /**< RGB 32 bpp UNORM R11 G11 B10 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, /**< Swapped RGB 32 bpp UNORM R11 G11 B10 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, /**< Floating point RGB 32 bpp R11 G11 B10 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, /**< Swapped Floating point RGB 32 bpp + R11 G11 B10 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE, /**< Shared Exponent RGB 32 bpp R9 G9 B9 E5 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, /**< Start of YCbCr formats. Used internally.*/ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = + VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, /**< Planar YUV 4:2:0 8 bpc Y Cb Cr, AKA NV12*/ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, /**< Semi-Planar YUV 4:2:0 8 bpc Y Cr Cb, AKA + NV21 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, /**< Semi-Planar YUV 4:2:0 10 bpc Y Cb Cr, AKA + P010 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, /**< Semi-Planar YUV 4:2:0 10 bpc Y Cr Cb */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb, /**< Semi-Planar YUV 4:2:0 12 bpc Y Cr Cb */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr, /**< Semi-Planar YUV 4:2:0 12 bpc Y Cb Cr, AKA + P016 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb, /**< Packed YUV 4:2:2 8 bpc Y Cr Y Cb */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr, /**< Packed YUV 4:2:2 8 bpc Y Cb Y Cr */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY, /**< Packed YUV 4:2:2 8 bpc Cr Y Cb Y */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY, /**< Packed YUV 4:2:2 8 bpc Cb Y Cr Y */ + VPE_SURFACE_PIXEL_FORMAT_SUBSAMPLE_END = + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY, /**< End of chroma sub-sampled formats. Used + internally */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, /**< Y410 32 bpp A2 Cr10 Y10 Cb10 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, /**< A-rotated Y410 32 bpp Cr10 Y10 Cb10 A2 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, /**< AYUV 32 bpp 8 bpc A8 Y8 Cr8 Cb8 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888, /**< A-rotated AYUV 32 bpp 8 bpc Y8 Cr8 Cb8 A8 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888, /**< Cr first AYUV 32 bpp 8 bpc A8 Cr8 Y8 Cb8 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888, /**< Alpha rotated Cr first AYUV 32 bpp 8 bpc + Cr8 Y8 Cb8 A8 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, /**< AYUV 32 bpp 8 bpc A8 Y8 Cb8 Cbr */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_END = + VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, /**< End of YCbCr formats. Used internally. */ + VPE_SURFACE_PIXEL_FORMAT_INVALID /**< Used for the formats which are not among + the recognized formats. */ }; /** @enum vpe_swizzle_mode_values diff --git a/src/amd/vpelib/inc/vpe_types.h b/src/amd/vpelib/inc/vpe_types.h index 32b7c6b56c6..08401e59520 100644 --- a/src/amd/vpelib/inc/vpe_types.h +++ b/src/amd/vpelib/inc/vpe_types.h @@ -47,7 +47,7 @@ struct vpe; * VPE library supports up to 8 taps and 64 phases, only (32+1) phases needed */ #define MAX_NB_POLYPHASE_COEFFS (8 * 33) - + /** @enum vpe_status * @brief The status of VPE to indicate whether it supports the given job or not. */ @@ -55,7 +55,7 @@ enum vpe_status { VPE_STATUS_OK = 1, /**< VPE supports the job. */ VPE_STATUS_ERROR, /**< Unknown Error in VPE. */ VPE_STATUS_NO_MEMORY, /**< VPE is out of memory. */ - VPE_STATUS_NOT_SUPPORTED, /**< VPE is out of memory. */ + VPE_STATUS_NOT_SUPPORTED, /**< VPE is not supported. */ VPE_STATUS_INPUT_DCC_NOT_SUPPORTED, /**< Input DCC is not supported. */ VPE_STATUS_OUTPUT_DCC_NOT_SUPPORTED, /**< Output DCC is not supported. */ VPE_STATUS_SWIZZLE_NOT_SUPPORTED, /**< Swizzle mode is not supported. */ @@ -251,6 +251,12 @@ struct vpe_caps { struct vpe_color_caps color_caps; /**< Color management caps */ struct vpe_plane_caps plane_caps; /**< Plane capabilities */ + struct { + uint32_t opaque : 1; + uint32_t bg_color : 1; + uint32_t destination : 1; + uint32_t source_stream : 1; + } alpha_fill_caps; }; /*********************************** @@ -429,7 +435,7 @@ struct vpe_debug_options { /** Struct to specify whether the debug flag for that * corresponding field should be honored. */ - struct { + struct { uint32_t cm_in_bypass : 1; /**< Color management bypass */ uint32_t vpcnvc_bypass : 1; /**< VPCNVC bypass */ uint32_t mpc_bypass : 1; /**< MPC bypass */ @@ -479,14 +485,14 @@ struct vpe_debug_options { uint32_t skip_optimal_tap_check : 1; /**< Skip optimal tap check */ uint32_t disable_lut_caching : 1; /**< disable config caching for all luts */ uint32_t disable_performance_mode : 1; /**< disable performance mode */ - uint32_t bg_bit_depth; /**< Background color bit depth. */ + uint32_t bg_bit_depth; /**< Background color bit depth. */ struct vpe_mem_low_power_enable_options - enable_mem_low_power; /**< Component activation on low power mode. Only used for debugging. + enable_mem_low_power; /**< Component activation on low power mode. Only used for debugging. */ - enum vpe_expansion_mode expansion_mode; - struct vpe_clamping_params clamping_params; - struct vpe_visual_confirm visual_confirm_params; + enum vpe_expansion_mode expansion_mode; /**< Color component expansion mode */ + struct vpe_clamping_params clamping_params; /**< Color clamping */ + struct vpe_visual_confirm visual_confirm_params; /**< Visual confirm bar parameters */ }; /** @struct vpe_init_data @@ -543,6 +549,7 @@ enum vpe_color_primaries { VPE_PRIMARIES_BT709, /**< BT. 709, Rec. 709 */ VPE_PRIMARIES_BT2020, /**< BT. 2020, Rec. 2020 */ VPE_PRIMARIES_JFIF, /**< JPEG File Interchange Format */ + VPE_PRIMARIES_CUSTOM, /**< Custom / user controlled */ VPE_PRIMARIES_COUNT }; @@ -558,6 +565,7 @@ enum vpe_transfer_function { VPE_TF_HLG, /**< Hybrid Log-Gamma */ VPE_TF_SRGB, /**< Standard RGB */ VPE_TF_BT709, /**< BT 709 */ + VPE_TF_CUSTOM, /**< Custom / user controlled */ VPE_TF_COUNT }; @@ -687,7 +695,6 @@ struct vpe_scaling_info { * If taps are set to 0, vpe internally calculates the * required number of taps based on the scaling ratio. */ - }; /** @struct vpe_scaling_filter_coeffs @@ -752,14 +759,9 @@ struct vpe_tonemap_params { uint16_t input_pq_norm_factor; /**< Perceptual Quantizer normalization factor. */ uint16_t lut_dim; /**< Size of one dimension of the 3D-LUT data*/ - uint16_t lut_container_dim; /**< Size of one dimension of the 3D-LUT container*/ - /** @brief 3D LUT settings - */ - union { - uint16_t *lut_data; /**< Accessible to CPU */ - }; - bool is_dma_lut; /**< Set to true if the 3D LUT is DMA LUT */ - bool enable_3dlut; /**< Enable/Disable 3D-LUT */ + uint16_t lut_container_dim; /**< Size of one dimension of the 3D-LUT container*/ + uint16_t *lut_data; /**< Accessible to CPU */ + bool enable_3dlut; /**< Enable/Disable 3D-LUT */ }; /** @enum vpe_keyer_mode @@ -789,6 +791,7 @@ struct vpe_color_keyer { float lower_a_bound; /**< Alpha Low Bound. Program 0.0f if no alpha channel in input format.*/ float upper_a_bound; /**< Alpha High Bound. Program 1.0f if no alpha channel in input format.*/ }; + /** @struct vpe_stream * @brief Input stream/frame properties to be passed to vpelib */ diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h index e8388e6d0d3..6f8b85fe2a2 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h @@ -66,6 +66,9 @@ uint16_t vpe10_get_bg_stream_idx(struct vpe_priv *vpe_priv); enum vpe_status vpe10_calculate_segments( struct vpe_priv *vpe_priv, const struct vpe_build_param *params); +uint32_t vpe10_get_max_seg_width(struct output_ctx *output_ctx, + enum vpe_surface_pixel_format format, enum vpe_scan_direction scan); + int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, uint32_t cmd_input_idx, bool seg_only); @@ -103,6 +106,9 @@ struct cdc_be *vpe10_cdc_be_create(struct vpe_priv *vpe_priv, int inst); bool vpe10_validate_cached_param(struct vpe_priv *vpe_priv, const struct vpe_build_param *param); +enum vpe_status vpe10_check_alpha_fill_support( + struct vpe *vpe, const struct vpe_build_param *param); + void vpe10_setup_check_funcs(struct vpe_check_support_funcs *funcs); const struct vpe_caps *vpe10_get_capability(void); diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_background.c b/src/amd/vpelib/src/chip/vpe10/vpe10_background.c index 7dcd9a4d6a6..0acf49a3bc2 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_background.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_background.c @@ -55,7 +55,7 @@ bool vpe10_split_bg_gap(struct vpe_rect *gaps, const struct vpe_rect *target_rec if (num_gaps_t + gap_cnt > max_gaps) return false; - for (gap_idx = prev_idx; gap_idx < num_gaps_t + gap_cnt; gap_idx++) { + for (gap_idx = prev_idx; gap_idx < (uint16_t)(num_gaps_t + gap_cnt); gap_idx++) { gaps[gap_idx].y = gap_y; gaps[gap_idx].height = gap_height; gaps[gap_idx].x = gap_x; diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c b/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c index c9477db0982..db1d4d4724b 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c @@ -1134,7 +1134,8 @@ void vpe10_mpc_program_1dlut(struct mpc *mpc, const struct pwl_params *params, e PROGRAM_ENTRY(); if ((params == NULL) || - (vpe_priv->init.debug.bypass_blndgam == true)) { // the bypass flag is used in debug mode to skip this block entirely + (vpe_priv->init.debug.bypass_blndgam == + true)) { // the bypass flag is used in debug mode to skip this block entirely REG_SET(VPMPCC_MCM_1DLUT_CONTROL, REG_DEFAULT(VPMPCC_MCM_1DLUT_CONTROL), VPMPCC_MCM_1DLUT_MODE, 0); diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c index 0110e389b6c..956b6158ca0 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c @@ -225,6 +225,13 @@ static struct vpe_caps .addr_alignment = 256, .max_viewport_width = 1024, }, + .alpha_fill_caps = + { + .opaque = 1, + .bg_color = 1, + .destination = 0, + .source_stream = 0, + }, }; static bool vpe10_init_scaler_data(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, @@ -428,6 +435,7 @@ enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resou res->check_h_mirror_support = vpe10_check_h_mirror_support; res->calculate_segments = vpe10_calculate_segments; + res->get_max_seg_width = vpe10_get_max_seg_width; res->set_num_segments = vpe10_set_num_segments; res->split_bg_gap = vpe10_split_bg_gap; res->calculate_dst_viewport_and_active = vpe10_calculate_dst_viewport_and_active; @@ -444,7 +452,8 @@ enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resou res->update_blnd_gamma = vpe10_update_blnd_gamma; res->update_output_gamma = vpe10_update_output_gamma; res->validate_cached_param = vpe10_validate_cached_param; - res->calculate_shaper = vpe10_calculate_shaper; + res->check_alpha_fill_support = vpe10_check_alpha_fill_support; + res->calculate_shaper = vpe10_calculate_shaper; return VPE_STATUS_OK; err: @@ -669,7 +678,7 @@ enum vpe_status vpe10_calculate_segments( const uint32_t max_lb_size = dpp->funcs->get_line_buffer_size(); uint16_t alignment = 1; - for (stream_idx = 0; stream_idx < vpe_priv->num_streams; stream_idx++) { + for (stream_idx = 0; stream_idx < (uint16_t)vpe_priv->num_streams; stream_idx++) { stream_ctx = &vpe_priv->stream_ctx[stream_idx]; src_rect = &stream_ctx->stream.scaling_info.src_rect; dst_rect = &stream_ctx->stream.scaling_info.dst_rect; @@ -697,6 +706,9 @@ enum vpe_status vpe10_calculate_segments( continue; } + max_seg_width = vpe_priv->resource.get_max_seg_width(&vpe_priv->output_ctx, + stream_ctx->stream.surface_info.format, VPE_SCAN_PATTERN_0_DEGREE); + /* If the source frame size in either dimension is 1 then the scaling ratio becomes 0 * in that dimension. If destination frame size in any dimesnion is 1 the scaling ratio * is NAN. @@ -740,8 +752,6 @@ enum vpe_status vpe10_calculate_segments( } } - max_seg_width = vpe_priv->pub.caps->plane_caps.max_viewport_width; - max_gaps = get_max_gap_num(vpe_priv, params, max_seg_width); gaps = vpe_zalloc(sizeof(struct vpe_rect) * max_gaps); @@ -769,64 +779,10 @@ enum vpe_status vpe10_calculate_segments( return res; } -static void build_clamping_params( - struct opp *opp, struct clamping_and_pixel_encoding_params *clamping) +uint32_t vpe10_get_max_seg_width(struct output_ctx *output_ctx, + enum vpe_surface_pixel_format format, enum vpe_scan_direction scan) { - struct vpe_priv *vpe_priv = opp->vpe_priv; - struct vpe_surface_info *dst_surface = &vpe_priv->output_ctx.surface; - enum vpe_color_range output_range = dst_surface->cs.range; - - memset(clamping, 0, sizeof(*clamping)); - clamping->clamping_level = CLAMPING_FULL_RANGE; - clamping->c_depth = vpe_get_color_depth(dst_surface->format); - if (output_range == VPE_COLOR_RANGE_STUDIO) { - if (!vpe_priv->init.debug.clamping_setting) { - switch (clamping->c_depth) { - case COLOR_DEPTH_888: - clamping->clamping_level = CLAMPING_LIMITED_RANGE_8BPC; - break; - case COLOR_DEPTH_101010: - clamping->clamping_level = CLAMPING_LIMITED_RANGE_10BPC; - break; - case COLOR_DEPTH_121212: - clamping->clamping_level = CLAMPING_LIMITED_RANGE_12BPC; - break; - default: - clamping->clamping_level = - CLAMPING_FULL_RANGE; // for all the others bit depths set the full range - break; - } - } else { - switch (vpe_priv->init.debug.clamping_params.clamping_range) { - case VPE_CLAMPING_LIMITED_RANGE_8BPC: - clamping->clamping_level = CLAMPING_LIMITED_RANGE_8BPC; - break; - case VPE_CLAMPING_LIMITED_RANGE_10BPC: - clamping->clamping_level = CLAMPING_LIMITED_RANGE_10BPC; - break; - case VPE_CLAMPING_LIMITED_RANGE_12BPC: - clamping->clamping_level = CLAMPING_LIMITED_RANGE_12BPC; - break; - default: - clamping->clamping_level = - CLAMPING_LIMITED_RANGE_PROGRAMMABLE; // for all the others set to programmable - // range - clamping->r_clamp_component_lower = - vpe_priv->output_ctx.clamping_params.r_clamp_component_lower; - clamping->g_clamp_component_lower = - vpe_priv->output_ctx.clamping_params.g_clamp_component_lower; - clamping->b_clamp_component_lower = - vpe_priv->output_ctx.clamping_params.b_clamp_component_lower; - clamping->r_clamp_component_upper = - vpe_priv->output_ctx.clamping_params.r_clamp_component_upper; - clamping->g_clamp_component_upper = - vpe_priv->output_ctx.clamping_params.g_clamp_component_upper; - clamping->b_clamp_component_upper = - vpe_priv->output_ctx.clamping_params.b_clamp_component_upper; - break; - } - } - } + return caps.plane_caps.max_viewport_width; } static enum mpcc_blend_mode get_blend_mode( @@ -1024,7 +980,7 @@ int32_t vpe10_program_backend( opp->funcs->program_pipe_control(opp, &pipe_ctrl_param); display_color_depth = vpe_get_color_depth(surface_info->format); - build_clamping_params(opp, &clamp_param); + vpe_build_clamping_params(opp, &clamp_param); vpe_resource_build_bit_depth_reduction_params(opp, &fmt_bit_depth); // disable dynamic expansion for now as no use case @@ -1047,7 +1003,7 @@ enum vpe_status vpe10_populate_cmd_info(struct vpe_priv *vpe_priv) struct vpe_cmd_info cmd_info = {0}; enum lut3d_type lut3d_type; - for (stream_idx = 0; stream_idx < vpe_priv->num_streams; stream_idx++) { + for (stream_idx = 0; stream_idx < (uint16_t)vpe_priv->num_streams; stream_idx++) { stream_ctx = &vpe_priv->stream_ctx[stream_idx]; lut3d_type = vpe_get_stream_lut3d_type(stream_ctx); @@ -1536,6 +1492,33 @@ const struct vpe_caps *vpe10_get_capability(void) return ∩︀ } +enum vpe_status vpe10_check_alpha_fill_support(struct vpe *vpe, const struct vpe_build_param *param) +{ + struct vpe_priv *vpe_priv = container_of(vpe, struct vpe_priv, pub); + enum vpe_status status = VPE_STATUS_NOT_SUPPORTED; + + switch (param->alpha_mode) { + case VPE_ALPHA_OPAQUE: + if (vpe_priv->pub.caps->alpha_fill_caps.opaque) + status = VPE_STATUS_OK; + break; + case VPE_ALPHA_BGCOLOR: + if (vpe_priv->pub.caps->alpha_fill_caps.bg_color) + status = VPE_STATUS_OK; + break; + case VPE_ALPHA_DESTINATION: + if (vpe_priv->pub.caps->alpha_fill_caps.destination) + status = VPE_STATUS_OK; + break; + case VPE_ALPHA_SOURCE_STREAM: + if (vpe_priv->pub.caps->alpha_fill_caps.source_stream) + status = VPE_STATUS_OK; + break; + } + + return status; +} + void vpe10_setup_check_funcs(struct vpe_check_support_funcs *funcs) { funcs->check_input_format = vpe10_check_input_format; diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_vpe_desc_writer.c b/src/amd/vpelib/src/chip/vpe10/vpe10_vpe_desc_writer.c index a5ff81d746b..47703326f22 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_vpe_desc_writer.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_vpe_desc_writer.c @@ -46,9 +46,6 @@ enum vpe_status vpe10_vpe_desc_writer_init( writer->base_gpu_va = buf->gpu_va; writer->buf = buf; writer->num_config_desc = 0; -#ifdef VPE_REGISTER_PROFILE - writer->reuse_num_config_dec = 0; -#endif writer->plane_desc_added = false; writer->status = VPE_STATUS_OK; @@ -126,10 +123,6 @@ void vpe10_vpe_desc_writer_add_config_desc( writer->buf->gpu_va += size; writer->buf->size -= size; writer->num_config_desc++; -#ifdef VPE_REGISTER_PROFILE - if (reuse) - writer->reuse_num_config_dec++; -#endif } void vpe10_vpe_desc_writer_complete(struct vpe_desc_writer *writer) diff --git a/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c b/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c index 33c855a68d9..c94d83200c2 100644 --- a/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c +++ b/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c @@ -59,7 +59,8 @@ reg##reg_name##_##DEFAULT, false} static struct vpe_caps - caps = { + caps = + { .max_input_size = { .width = 16384, @@ -158,6 +159,13 @@ static struct vpe_caps .addr_alignment = 256, .max_viewport_width = 1024, }, + .alpha_fill_caps = + { + .opaque = 1, + .bg_color = 1, + .destination = 0, + .source_stream = 0, + }, }; enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resource *res) @@ -198,6 +206,7 @@ enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resou res->check_h_mirror_support = vpe10_check_h_mirror_support; res->calculate_segments = vpe10_calculate_segments; + res->get_max_seg_width = vpe10_get_max_seg_width; res->set_num_segments = vpe11_set_num_segments; res->split_bg_gap = vpe10_split_bg_gap; res->calculate_dst_viewport_and_active = vpe10_calculate_dst_viewport_and_active; @@ -214,7 +223,8 @@ enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resou res->update_blnd_gamma = vpe10_update_blnd_gamma; res->update_output_gamma = vpe10_update_output_gamma; res->validate_cached_param = vpe11_validate_cached_param; - res->calculate_shaper = vpe10_calculate_shaper; + res->check_alpha_fill_support = vpe10_check_alpha_fill_support; + res->calculate_shaper = vpe10_calculate_shaper; return VPE_STATUS_OK; err: diff --git a/src/amd/vpelib/src/chip/vpe11/vpe11_vpe_desc_writer.c b/src/amd/vpelib/src/chip/vpe11/vpe11_vpe_desc_writer.c index f295adbc0c8..1fc17da2008 100644 --- a/src/amd/vpelib/src/chip/vpe11/vpe11_vpe_desc_writer.c +++ b/src/amd/vpelib/src/chip/vpe11/vpe11_vpe_desc_writer.c @@ -47,9 +47,6 @@ enum vpe_status vpe11_vpe_desc_writer_init( writer->base_gpu_va = buf->gpu_va; writer->buf = buf; writer->num_config_desc = 0; -#ifdef VPE_REGISTER_PROFILE - writer->reuse_num_config_dec = 0; -#endif writer->plane_desc_added = false; writer->status = VPE_STATUS_OK; diff --git a/src/amd/vpelib/src/core/color.c b/src/amd/vpelib/src/core/color.c index 33865afdb2f..ae537d7b517 100644 --- a/src/amd/vpelib/src/core/color.c +++ b/src/amd/vpelib/src/core/color.c @@ -195,6 +195,7 @@ static enum vpe_status vpe_allocate_cm_memory( } output_ctx = &vpe_priv->output_ctx; + if (!output_ctx->output_tf) { output_ctx->output_tf = (struct transfer_func *)vpe_zalloc(sizeof(struct transfer_func)); if (!output_ctx->output_tf) { diff --git a/src/amd/vpelib/src/core/common.c b/src/amd/vpelib/src/core/common.c index c8251b32eed..5e07f7a7df8 100644 --- a/src/amd/vpelib/src/core/common.c +++ b/src/amd/vpelib/src/core/common.c @@ -159,8 +159,8 @@ bool vpe_is_yuv420_10(enum vpe_surface_pixel_format format) bool vpe_is_yuv420_16(enum vpe_surface_pixel_format format) { switch (format) { - case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCrCb: - case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: return true; default: return false; @@ -290,7 +290,6 @@ enum color_depth vpe_get_color_depth(enum vpe_surface_pixel_format format) case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: - case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCrCb: c_depth = COLOR_DEPTH_161616; break; default: @@ -620,8 +619,9 @@ enum vpe_status vpe_check_tone_map_support( status = VPE_STATUS_BAD_TONE_MAP_PARAMS; } } else { - if (is_hlg || - (input_is_hdr && is_in_lum_greater_than_out_lum)) { + if ((is_hlg == true) || + ((input_is_hdr == true) && (is_in_lum_greater_than_out_lum == true) && + (stream->flags.geometric_scaling == false))) { status = VPE_STATUS_BAD_TONE_MAP_PARAMS; } } diff --git a/src/amd/vpelib/src/core/config_writer.c b/src/amd/vpelib/src/core/config_writer.c index c2f1b929577..3c0f4dbbd77 100644 --- a/src/amd/vpelib/src/core/config_writer.c +++ b/src/amd/vpelib/src/core/config_writer.c @@ -68,6 +68,7 @@ static inline void config_writer_new(struct config_writer *writer) if (writer->status != VPE_STATUS_OK) return; + // For VPE 2.0 all config and plane descriptors gpu address must be 6 bit aligned uint16_t alignment = writer->gpu_addr_alignment; uint64_t aligned_gpu_address = (writer->buf->gpu_va + alignment) & ~alignment; uint64_t alignment_offset = aligned_gpu_address - writer->buf->gpu_va; @@ -103,7 +104,8 @@ void config_writer_set_type(struct config_writer *writer, enum config_type type, if (writer->status != VPE_STATUS_OK) return; - if ((writer->type != type) || (writer->pipe_idx != pipe_idx)) { + if ((writer->type != type) || ((writer->pipe_idx != pipe_idx) + )) { if (writer->type == CONFIG_TYPE_UNKNOWN) { // new header or only pipe change. do not need to fill it yet until completion writer->pipe_idx = pipe_idx; @@ -207,14 +209,6 @@ void config_writer_fill_direct_config_packet_header( return; } -#ifdef VPE_REGISTER_PROFILE - writer->total_register_count += packet->bits.VPEP_CONFIG_DATA_SIZE + 1; - if (packet->bits.VPEP_CONFIG_DATA_SIZE == 0) { - writer->nonBurstMode_register_count++; - } else { - writer->burstMode_register_count += packet->bits.VPEP_CONFIG_DATA_SIZE + 1; - } -#endif cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; *cmd_space++ = packet->u32all; writer->buf->cpu_va += w_size; @@ -249,10 +243,6 @@ void config_writer_fill_direct_config_packet( return; } -#ifdef VPE_REGISTER_PROFILE - writer->total_register_count++; - writer->nonBurstMode_register_count++; -#endif cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; *cmd_space++ = packet->u32all; // Write header writer->buf->cpu_va += sizeof(uint32_t); diff --git a/src/amd/vpelib/src/core/inc/config_writer.h b/src/amd/vpelib/src/core/inc/config_writer.h index 985cf72ac71..1ebc1033920 100644 --- a/src/amd/vpelib/src/core/inc/config_writer.h +++ b/src/amd/vpelib/src/core/inc/config_writer.h @@ -40,7 +40,7 @@ extern "C" { enum config_type { CONFIG_TYPE_UNKNOWN, CONFIG_TYPE_DIRECT, - CONFIG_TYPE_INDIRECT + CONFIG_TYPE_INDIRECT, }; typedef void (*config_callback_t)( @@ -92,13 +92,6 @@ struct config_writer { config_callback_t callback; enum vpe_status status; -#ifdef VPE_REGISTER_PROFILE - uint64_t total_register_count; - uint64_t burstMode_register_count; - uint64_t nonBurstMode_register_count; - uint64_t total_config_count; - uint64_t reused_config_count; -#endif }; /** initialize the config writer. diff --git a/src/amd/vpelib/src/core/inc/opp.h b/src/amd/vpelib/src/core/inc/opp.h index bd246cfae3e..3e01b646a9d 100644 --- a/src/amd/vpelib/src/core/inc/opp.h +++ b/src/amd/vpelib/src/core/inc/opp.h @@ -128,6 +128,7 @@ struct opp_funcs { void (*program_pipe_control)(struct opp *opp, const struct opp_pipe_control_params *params); void (*program_pipe_crc)(struct opp *opp, bool enable); + }; struct opp { diff --git a/src/amd/vpelib/src/core/inc/reg_helper.h b/src/amd/vpelib/src/core/inc/reg_helper.h index 5400b82bca9..8a4a987181f 100644 --- a/src/amd/vpelib/src/core/inc/reg_helper.h +++ b/src/amd/vpelib/src/core/inc/reg_helper.h @@ -231,6 +231,27 @@ typedef struct reg_id_val { config_writer_fill_direct_config_packet(config_writer, &packet); \ } while (0) +#define REG_SET_11(reg_name, init_val, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, \ + v8, f9, v9, f10, v10, f11, v11) \ + do { \ + packet.bits.INC = 0; \ + packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \ + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(reg_name); \ + REG_IS_WRITTEN(reg_name) = true; \ + packet.data[0] = REG_LAST_WRITTEN_VAL(reg_name) = \ + (((uint32_t)init_val & ~(REG_FIELD_MASK(f1)) & ~(REG_FIELD_MASK(f2)) & \ + ~(REG_FIELD_MASK(f3)) & ~(REG_FIELD_MASK(f4)) & ~(REG_FIELD_MASK(f5)) & \ + ~(REG_FIELD_MASK(f6)) & ~(REG_FIELD_MASK(f7)) & ~(REG_FIELD_MASK(f8)) & \ + ~(REG_FIELD_MASK(f9)) & ~(REG_FIELD_MASK(f10))) | \ + REG_FIELD_VALUE(f1, (uint32_t)v1) | REG_FIELD_VALUE(f2, (uint32_t)v2) | \ + REG_FIELD_VALUE(f3, (uint32_t)v3) | REG_FIELD_VALUE(f4, (uint32_t)v4) | \ + REG_FIELD_VALUE(f5, (uint32_t)v5) | REG_FIELD_VALUE(f6, (uint32_t)v6) | \ + REG_FIELD_VALUE(f7, (uint32_t)v7) | REG_FIELD_VALUE(f8, (uint32_t)v8) | \ + REG_FIELD_VALUE(f9, (uint32_t)v9) | REG_FIELD_VALUE(f10, (uint32_t)v10) | \ + REG_FIELD_VALUE(f11, (uint32_t)v11)); \ + config_writer_fill_direct_config_packet(config_writer, &packet); \ + } while (0) + #define REG_SET_DEFAULT(reg_name) \ do { \ packet.bits.INC = 0; \ diff --git a/src/amd/vpelib/src/core/inc/resource.h b/src/amd/vpelib/src/core/inc/resource.h index a90b152406f..bbe4015d3b7 100644 --- a/src/amd/vpelib/src/core/inc/resource.h +++ b/src/amd/vpelib/src/core/inc/resource.h @@ -43,6 +43,7 @@ struct vpe_priv; struct vpe_cmd_output; struct vpe_cmd_info; struct segment_ctx; +struct vpe_cmd_input; enum vpe_stream_type; #define MIN_VPE_CMD (1024) @@ -69,6 +70,9 @@ struct resource { enum vpe_status (*calculate_segments)( struct vpe_priv *vpe_priv, const struct vpe_build_param *params); + uint32_t (*get_max_seg_width)(struct output_ctx *output_ctx, + enum vpe_surface_pixel_format format, enum vpe_scan_direction scan); + enum vpe_status(*check_bg_color_support)(struct vpe_priv* vpe_priv, struct vpe_color* bg_color); void (*bg_color_convert)(enum color_space output_cs, struct transfer_func *output_tf, @@ -115,6 +119,9 @@ struct resource { bool (*validate_cached_param)(struct vpe_priv *vpe_priv, const struct vpe_build_param *param); + enum vpe_status (*check_alpha_fill_support)( + struct vpe *vpe, const struct vpe_build_param *param); + enum vpe_status (*calculate_shaper)(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx); // Indicates the nominal range hdr input content should be in during processing. @@ -177,6 +184,9 @@ void vpe_handle_output_h_mirror(struct vpe_priv *vpe_priv); void vpe_resource_build_bit_depth_reduction_params( struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth); +void vpe_build_clamping_params( + struct opp *opp, struct clamping_and_pixel_encoding_params *clamping); + /** resource function call backs*/ void vpe_frontend_config_callback( void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, uint64_t size, uint32_t pipe_idx); diff --git a/src/amd/vpelib/src/core/inc/vpe_command.h b/src/amd/vpelib/src/core/inc/vpe_command.h index c45ee871850..bde5b741e31 100644 --- a/src/amd/vpelib/src/core/inc/vpe_command.h +++ b/src/amd/vpelib/src/core/inc/vpe_command.h @@ -87,8 +87,8 @@ enum VPE_CMD_OPCODE { * VPEP Config ************************/ enum VPE_VPEP_CFG_SUBOP { - VPE_VPEP_CFG_SUBOP_DIR_CFG = 0x0, - VPE_VPEP_CFG_SUBOP_IND_CFG = 0x1 + VPE_VPEP_CFG_SUBOP_DIR_CFG = 0x0, + VPE_VPEP_CFG_SUBOP_IND_CFG = 0x1, }; // Direct Config Command Header diff --git a/src/amd/vpelib/src/core/inc/vpe_desc_writer.h b/src/amd/vpelib/src/core/inc/vpe_desc_writer.h index 88b8ef5d119..47ec75a793e 100644 --- a/src/amd/vpelib/src/core/inc/vpe_desc_writer.h +++ b/src/amd/vpelib/src/core/inc/vpe_desc_writer.h @@ -41,9 +41,6 @@ struct vpe_desc_writer { uint64_t base_cpu_va; uint32_t num_config_desc; -#ifdef VPE_REGISTER_PROFILE - uint32_t reuse_num_config_dec; -#endif bool plane_desc_added; enum vpe_status status; diff --git a/src/amd/vpelib/src/core/inc/vpe_priv.h b/src/amd/vpelib/src/core/inc/vpe_priv.h index 76eb6e466fc..42fd7485ac4 100644 --- a/src/amd/vpelib/src/core/inc/vpe_priv.h +++ b/src/amd/vpelib/src/core/inc/vpe_priv.h @@ -200,7 +200,6 @@ struct output_ctx { }; unsigned int u32All; } dirty_bits; - struct transfer_func *output_tf; const struct transfer_func *in_shaper_func; // for shaper lut const struct vpe_3dlut *lut3d_func; // for 3dlut @@ -280,7 +279,7 @@ struct vpe_priv { uint16_t vpe_num_instance; bool collaboration_mode; enum vpe_expansion_mode expansion_mode; - const struct vpe_engine *engine_handle; /**< vpe engine instance */ + const struct vpe_engine *engine_handle; /**< vpe engine instance */ }; /** internal vpe engine instance */ @@ -288,10 +287,10 @@ struct vpe_engine_priv { struct vpe_engine pub; /**< public member */ /** internal */ - struct vpe_init_data init; /**< vpe init data */ - uint8_t ver_major; /**< vpe major version */ - uint8_t ver_minor; /**< vpe minor version */ - uint8_t ver_rev; /**< vpe revision version */ + struct vpe_init_data init; /**< vpe init data */ + uint8_t ver_major; /**< vpe major version */ + uint8_t ver_minor; /**< vpe minor version */ + uint8_t ver_rev; /**< vpe revision version */ }; #ifdef __cplusplus } diff --git a/src/amd/vpelib/src/core/resource.c b/src/amd/vpelib/src/core/resource.c index a86e25cf1a5..11afdd8aca4 100644 --- a/src/amd/vpelib/src/core/resource.c +++ b/src/amd/vpelib/src/core/resource.c @@ -94,6 +94,7 @@ enum vpe_ip_level vpe_resource_parse_ip_version( ip_level = VPE_IP_LEVEL_UNKNOWN; break; } + return ip_level; } @@ -608,7 +609,8 @@ static enum vpe_status calculate_inits_and_viewports(struct segment_ctx *segment enum lut3d_type vpe_get_stream_lut3d_type(struct stream_ctx *stream_ctx) { enum lut3d_type lut3d; - + // lut3d_type holds the 3dlut type NONE, CPU (Direct Config), or GPU (Fast Load) + // for Fast Load Enable/Disable if ((stream_ctx->stream.tm_params.UID == 0) || (!stream_ctx->stream.tm_params.enable_3dlut)) { lut3d = LUT3D_TYPE_NONE; } else { @@ -734,7 +736,7 @@ void vpe_handle_output_h_mirror(struct vpe_priv *vpe_priv) struct stream_ctx *stream_ctx; // swap the stream output location - for (stream_idx = 0; stream_idx < vpe_priv->num_streams; stream_idx++) { + for (stream_idx = 0; stream_idx < (uint16_t)vpe_priv->num_streams; stream_idx++) { stream_ctx = &vpe_priv->stream_ctx[stream_idx]; if (stream_ctx->flip_horizonal_output) { struct segment_ctx *first_seg, *last_seg; @@ -787,6 +789,65 @@ void vpe_resource_build_bit_depth_reduction_params( } } +void vpe_build_clamping_params(struct opp *opp, struct clamping_and_pixel_encoding_params *clamping) +{ + struct vpe_priv *vpe_priv = opp->vpe_priv; + struct vpe_surface_info *dst_surface = &vpe_priv->output_ctx.surface; + enum vpe_color_range output_range = dst_surface->cs.range; + + memset(clamping, 0, sizeof(*clamping)); + clamping->clamping_level = CLAMPING_FULL_RANGE; + clamping->c_depth = vpe_get_color_depth(dst_surface->format); + if (output_range == VPE_COLOR_RANGE_STUDIO) { + if (!vpe_priv->init.debug.clamping_setting) { + switch (clamping->c_depth) { + case COLOR_DEPTH_888: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_8BPC; + break; + case COLOR_DEPTH_101010: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_10BPC; + break; + case COLOR_DEPTH_121212: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_12BPC; + break; + default: + clamping->clamping_level = + CLAMPING_FULL_RANGE; // for all the others bit depths set the full range + break; + } + } else { + switch (vpe_priv->init.debug.clamping_params.clamping_range) { + case VPE_CLAMPING_LIMITED_RANGE_8BPC: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_8BPC; + break; + case VPE_CLAMPING_LIMITED_RANGE_10BPC: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_10BPC; + break; + case VPE_CLAMPING_LIMITED_RANGE_12BPC: + clamping->clamping_level = CLAMPING_LIMITED_RANGE_12BPC; + break; + default: + clamping->clamping_level = + CLAMPING_LIMITED_RANGE_PROGRAMMABLE; // for all the others set to programmable + // range + clamping->r_clamp_component_lower = + vpe_priv->output_ctx.clamping_params.r_clamp_component_lower; + clamping->g_clamp_component_lower = + vpe_priv->output_ctx.clamping_params.g_clamp_component_lower; + clamping->b_clamp_component_lower = + vpe_priv->output_ctx.clamping_params.b_clamp_component_lower; + clamping->r_clamp_component_upper = + vpe_priv->output_ctx.clamping_params.r_clamp_component_upper; + clamping->g_clamp_component_upper = + vpe_priv->output_ctx.clamping_params.g_clamp_component_upper; + clamping->b_clamp_component_upper = + vpe_priv->output_ctx.clamping_params.b_clamp_component_upper; + break; + } + } + } +} + void vpe_frontend_config_callback( void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, uint64_t size, uint32_t pipe_idx) { diff --git a/src/amd/vpelib/src/core/vpe_visual_confirm.c b/src/amd/vpelib/src/core/vpe_visual_confirm.c index 83f1d69fba3..cf8b2407e51 100644 --- a/src/amd/vpelib/src/core/vpe_visual_confirm.c +++ b/src/amd/vpelib/src/core/vpe_visual_confirm.c @@ -68,7 +68,7 @@ static uint16_t vpe_get_visual_confirm_total_seg_count( uint32_t alignment = vpe_get_recout_width_alignment(params); if (vpe_priv->init.debug.visual_confirm_params.input_format) { - for (stream_idx = 0; stream_idx < vpe_priv->num_streams; stream_idx++) { + for (stream_idx = 0; stream_idx < (uint16_t)vpe_priv->num_streams; stream_idx++) { stream_ctx = &vpe_priv->stream_ctx[stream_idx]; if (should_generate_visual_confirm(stream_ctx->stream_type)) total_visual_confirm_segs += get_visual_confirm_segs_count( @@ -209,7 +209,7 @@ enum vpe_status vpe_create_visual_confirm_segs( // Do visual confirm bg generation for input format if (vpe_priv->init.debug.visual_confirm_params.input_format && params->target_rect.height > 2 * VISUAL_CONFIRM_HEIGHT) { - for (stream_idx = 0; stream_idx < params->num_streams; stream_idx++) { + for (stream_idx = 0; stream_idx < (uint16_t)params->num_streams; stream_idx++) { stream_ctx = &vpe_priv->stream_ctx[stream_idx]; visual_confirm_rect = stream_ctx->stream.scaling_info.dst_rect; visual_confirm_rect.y += 0; diff --git a/src/amd/vpelib/src/core/vpelib.c b/src/amd/vpelib/src/core/vpelib.c index 4a3dcba54ea..c184d7bd6e4 100644 --- a/src/amd/vpelib/src/core/vpelib.c +++ b/src/amd/vpelib/src/core/vpelib.c @@ -132,6 +132,9 @@ static void override_debug_option( if (user_debug->flags.disable_lut_caching) debug->disable_lut_caching = user_debug->disable_lut_caching; + + if (user_debug->flags.disable_performance_mode) + debug->disable_performance_mode = user_debug->disable_performance_mode; } static void verify_collaboration_mode(struct vpe_priv *vpe_priv) @@ -144,7 +147,7 @@ static void verify_collaboration_mode(struct vpe_priv *vpe_priv) randnum = randnum << 12; vpe_priv->collaborate_sync_index = (int32_t)randnum; } - } else if (vpe_priv->pub.level == VPE_IP_LEVEL_1_0) { + } else { vpe_priv->collaboration_mode = false; } } @@ -448,7 +451,9 @@ static enum vpe_status populate_input_streams(struct vpe_priv *vpe_priv, const s if (vpe_priv->init.debug.bypass_per_pixel_alpha) { stream_ctx->per_pixel_alpha = false; - } else if (param->streams[i].enable_luma_key) { + } + else if (param->streams[i].enable_luma_key) + { stream_ctx->per_pixel_alpha = true; } if (param->streams[i].horizontal_mirror && !input_h_mirror && output_h_mirror) @@ -552,6 +557,13 @@ enum vpe_status vpe_check_support( status = VPE_STATUS_NO_MEMORY; } + if (status == VPE_STATUS_OK) { + // alpha fill checking - support alpha fill mode in different stage + status = vpe_priv->resource.check_alpha_fill_support(vpe, param); + if (status != VPE_STATUS_OK) { + vpe_log("fail alplha fill check. status %d\n", (int)status); + } + } if (status == VPE_STATUS_OK) { // output checking - check per asic support @@ -584,7 +596,6 @@ enum vpe_status vpe_check_support( } } - if (status == VPE_STATUS_OK) { // output resource preparation for further checking (cache the result) output_ctx = &vpe_priv->output_ctx; @@ -600,7 +611,6 @@ enum vpe_status vpe_check_support( output_ctx->clamping_params = vpe_priv->init.debug.clamping_params; } - if (status == VPE_STATUS_OK) { status = populate_input_streams(vpe_priv, param, vpe_priv->stream_ctx); if (status != VPE_STATUS_OK) @@ -692,13 +702,6 @@ enum vpe_status vpe_build_commands( vpe_priv = container_of(vpe, struct vpe_priv, pub); -#ifdef VPE_REGISTER_PROFILE - vpe_priv->config_writer.total_register_count = 0; - vpe_priv->config_writer.burstMode_register_count = 0; - vpe_priv->config_writer.nonBurstMode_register_count = 0; - vpe_priv->config_writer.total_config_count = 0; - vpe_priv->config_writer.reused_config_count = 0; -#endif if (!vpe_priv->ops_support) { if (vpe_priv->init.debug.assert_when_not_support) { VPE_ASSERT(vpe_priv->ops_support); @@ -841,20 +844,7 @@ enum vpe_status vpe_build_commands( } } } -#ifdef VPE_REGISTER_PROFILE - vpe_priv->config_writer.total_config_count += vpe_priv->vpe_desc_writer.num_config_desc; - vpe_priv->config_writer.reused_config_count += vpe_priv->vpe_desc_writer.reuse_num_config_dec; -#endif } -#ifdef VPE_REGISTER_PROFILE - vpe_log("Total Registers Accessed: % d\n", vpe_priv->config_writer.total_register_count); - vpe_log("Burst Mode Registers Accessed: % d\n", - vpe_priv->config_writer.burstMode_register_count); - vpe_log("Non-Burst Mode Registers Accessed: % d\n", - vpe_priv->config_writer.nonBurstMode_register_count); - vpe_log("Total Config Descriptors: % d\n", vpe_priv->config_writer.total_config_count); - vpe_log("Total Re-used Config Descriptors: % d\n", vpe_priv->config_writer.reused_config_count); -#endif if ((status == VPE_STATUS_OK) && (vpe_priv->collaboration_mode == true)) { status = builder->build_collaborate_sync_cmd(vpe_priv, &curr_bufs); if (status != VPE_STATUS_OK) { diff --git a/src/amd/vpelib/src/utils/conversion.c b/src/amd/vpelib/src/utils/conversion.c index e908261d73e..6715dd345e4 100644 --- a/src/amd/vpelib/src/utils/conversion.c +++ b/src/amd/vpelib/src/utils/conversion.c @@ -98,3 +98,22 @@ struct fixed31_32 vpe_convfix31_32(int16_t inval) result.value = -result.value; return result; } + +uint32_t vpe_float_to_S1n(float value, int N) +{ + float max_val = (float)(2.0 - 1.0 / (1 << N)); + float min_val = (float)-2.0; + + if (value > max_val) + value = max_val; + if (value < min_val) + value = min_val; + + uint32_t fixed_val; + // +- 0.5 for simple rounding + if (value * (1 << N) >= 0) + fixed_val = (int32_t)(value * (float)(1 << ((N < 0) ? 0 : N)) + 0.5); + else + fixed_val = (int32_t)(value * ((N < 0) ? 1.0f : (float)(1U << N)) - 0.5); + return fixed_val; +} diff --git a/src/amd/vpelib/src/utils/inc/conversion.h b/src/amd/vpelib/src/utils/inc/conversion.h index cad23c7ce5f..1785805aaeb 100644 --- a/src/amd/vpelib/src/utils/inc/conversion.h +++ b/src/amd/vpelib/src/utils/inc/conversion.h @@ -38,6 +38,8 @@ void conv_convert_float_matrix( struct fixed31_32 vpe_convfix31_32(int16_t inval); +uint32_t vpe_float_to_S1n(float value, int N); + #ifdef __cplusplus } #endif