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pan/bi: Lower FS input loads in NIR
Co-authored-by: Lorenzo Rossi <lorenzo.rossi@collabora.com> Reviewed-by: Lorenzo Rossi <lorenzo.rossi@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40391>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
d2f430bea9
commit
8541dca8ed
4 changed files with 127 additions and 148 deletions
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@ -580,151 +580,6 @@ bi_emit_load_attr(bi_builder *b, nir_intrinsic_instr *instr)
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bi_copy_component(b, instr, dest);
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}
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static void
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bi_emit_load_fs_input(bi_builder *b, nir_intrinsic_instr *instr)
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{
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enum bi_sample sample = BI_SAMPLE_CENTER;
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enum bi_update update = BI_UPDATE_STORE;
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enum bi_register_format regfmt = BI_REGISTER_FORMAT_AUTO;
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enum bi_source_format source_format;
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bool smooth = instr->intrinsic == nir_intrinsic_load_interpolated_input;
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bi_index src0 = bi_null();
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/* Only use LD_VAR_BUF[_IMM] if explicitly told by the driver
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* through a compiler input value, falling back to LD_VAR[_IMM] +
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* Attribute Descriptors otherwise. */
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bool use_ld_var_buf =
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b->shader->malloc_idvs && b->shader->inputs->valhall.use_ld_var_buf;
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unsigned component = nir_intrinsic_component(instr);
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enum bi_vecsize vecsize = (instr->num_components + component - 1);
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bi_index dest =
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(component == 0) ? bi_def_index(&instr->def) : bi_temp(b->shader);
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nir_io_semantics sem = nir_intrinsic_io_semantics(instr);
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const nir_alu_type type = nir_intrinsic_dest_type(instr);
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const nir_alu_type base_type = nir_alu_type_get_base_type(type);
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const nir_alu_type sz = nir_alu_type_get_type_size(type);
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assert(sz == instr->def.bit_size);
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assert(sz == 16 || sz == 32);
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assert(base_type == nir_type_int || base_type == nir_type_uint || base_type == nir_type_float);
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const struct pan_varying_slot *slot = NULL;
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unsigned src_sz = sz;
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if (use_ld_var_buf) {
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pan_varying_layout_require_layout(b->shader->varying_layout);
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slot = pan_varying_layout_find_slot(b->shader->varying_layout,
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sem.location);
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assert(slot);
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src_sz = nir_alu_type_get_type_size(slot->alu_type);
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assert(src_sz == 16 || src_sz == 32);
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}
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if (smooth) {
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nir_intrinsic_instr *parent = nir_src_as_intrinsic(instr->src[0]);
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assert(parent);
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sample = bi_interp_for_intrinsic(parent->intrinsic);
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src0 = bi_varying_src0_for_barycentric(b, parent);
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/* Smooth ints don't exist */
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assert(base_type == nir_type_float);
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regfmt = (sz == 16) ? BI_REGISTER_FORMAT_F16 : BI_REGISTER_FORMAT_F32;
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source_format =
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(src_sz == 16) ? BI_SOURCE_FORMAT_F16 : BI_SOURCE_FORMAT_F32;
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} else {
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if (use_ld_var_buf) {
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/* integer regfmt are not supported by LD_VAR_BUF, but using float src_types for integers
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* is okay if the source_format is flat and uses the same bit size.
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* The conversion is a no-op. */
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regfmt = (sz == 16) ? BI_REGISTER_FORMAT_F16 : BI_REGISTER_FORMAT_F32;
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source_format = (src_sz == 16) ?
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BI_SOURCE_FORMAT_FLAT16 : BI_SOURCE_FORMAT_FLAT32;
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/* conversion MUST be a noop for int varyings to work correctly */
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assert(base_type == nir_type_float || src_sz == sz);
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} else {
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/* Flat loading with i16/u16 is not encodable */
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assert(base_type == nir_type_float || sz == 32);
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regfmt = bi_reg_fmt_for_nir(type);
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}
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/* Valhall can't have bi_null() here, although the source is
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* logically unused for flat varyings
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*/
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if (b->shader->arch >= 9)
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src0 = bi_preload(b, 61);
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/* Gather info as we go */
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b->shader->info.bifrost->uses_flat_shading = true;
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}
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nir_src *offset_src = nir_get_io_offset_src(instr);
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unsigned imm_index = 0;
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bool immediate = bi_is_imm_var_desc_handle(b, instr, &imm_index);
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unsigned base = nir_intrinsic_base(instr);
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if (use_ld_var_buf) {
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assert(slot);
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if (immediate) {
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assert(nir_src_is_const(*offset_src) && "assumes immediate offset");
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unsigned offset = slot->offset + (nir_src_as_uint(*offset_src) * 16);
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/* Immediate index given in bytes. */
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bi_ld_var_buf_imm_to(b, sz, dest, src0, regfmt, sample, source_format,
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update, vecsize, offset);
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} else {
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bi_index idx = bi_src_index(offset_src);
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/* Index needs to be in bytes, but NIR gives the index
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* in slots. For now assume 16 bytes per element.
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*/
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bi_index idx_bytes = bi_lshift_or_i32(b, idx, bi_zero(), bi_imm_u8(4));
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if (slot->offset != 0)
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idx_bytes = bi_iadd_u32(b, idx_bytes, bi_imm_u32(slot->offset),
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false);
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bi_ld_var_buf_to(b, sz, dest, src0, idx_bytes, regfmt, sample,
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source_format, update, vecsize);
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}
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} else {
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/* On Valhall, ensure the table and index are valid for usage with
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* immediate form when IDVS isn't used */
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if (b->shader->arch >= 9)
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immediate &= va_is_valid_const_table(pan_res_handle_get_table(base)) &&
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pan_res_handle_get_index(base) < 256;
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if (immediate) {
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bi_instr *I;
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if (smooth) {
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I = bi_ld_var_imm_to(b, dest, src0, regfmt, sample, update, vecsize,
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pan_res_handle_get_index(imm_index));
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} else {
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I =
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bi_ld_var_flat_imm_to(b, dest, BI_FUNCTION_NONE, regfmt, vecsize,
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pan_res_handle_get_index(imm_index));
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}
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/* Valhall usually uses LD_VAR_BUF. If this is disabled, use a simple
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* Midgard-style ABI. */
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if (b->shader->arch >= 9)
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I->table = va_res_fold_table_idx(pan_res_handle_get_table(base));
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} else {
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bi_index idx = bi_src_index(offset_src);
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if (base != 0)
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idx = bi_iadd_u32(b, idx, bi_imm_u32(base), false);
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if (smooth)
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bi_ld_var_to(b, dest, src0, idx, regfmt, sample, update, vecsize);
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else
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bi_ld_var_flat_to(b, dest, idx, BI_FUNCTION_NONE, regfmt, vecsize);
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}
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}
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bi_copy_component(b, instr, dest);
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}
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static void
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bi_emit_load_var(bi_builder *b, nir_intrinsic_instr *intr)
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{
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@ -2140,9 +1995,7 @@ bi_emit_intrinsic(bi_builder *b, nir_intrinsic_instr *instr)
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case nir_intrinsic_load_interpolated_input:
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case nir_intrinsic_load_input:
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assert(!b->shader->inputs->is_blend);
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if (stage == MESA_SHADER_FRAGMENT)
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bi_emit_load_fs_input(b, instr);
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else if (stage == MESA_SHADER_VERTEX)
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if (stage == MESA_SHADER_VERTEX)
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bi_emit_load_attr(b, instr);
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else
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UNREACHABLE("Unsupported shader stage");
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@ -7247,6 +7100,10 @@ bifrost_compile_shader_nir(nir_shader *nir,
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inputs->trust_varying_flat_highp_types, false);
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info->varyings.noperspective =
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pan_nir_collect_noperspective_varyings_fs(nir);
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if (!inputs->is_blend)
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NIR_PASS(_, nir, pan_nir_lower_fs_inputs, inputs->gpu_id,
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inputs->varying_layout, inputs->valhall.use_ld_var_buf);
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}
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if (nir->info.stage == MESA_SHADER_VERTEX && info->vs.idvs) {
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@ -16,6 +16,7 @@ libpanfrost_compiler_files = files(
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'pan_nir_lower_sample_position.c',
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'pan_nir_lower_store_component.c',
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'pan_nir_lower_texel_buffer_index.c',
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'pan_nir_lower_varyings_io.c',
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'pan_nir_lower_vertex_id.c',
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'pan_nir_lower_xfb.c',
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'pan_nir_resize_varying_io.c',
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@ -57,6 +57,10 @@ bool pan_nir_lower_frag_coord_zw(nir_shader *shader);
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bool pan_nir_lower_noperspective_vs(nir_shader *shader);
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bool pan_nir_lower_noperspective_fs(nir_shader *shader);
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bool pan_nir_lower_fs_inputs(nir_shader *shader, unsigned gpu_id,
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const struct pan_varying_layout *varying_layout,
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bool valhall_use_ld_var_buf);
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bool pan_nir_lower_helper_invocation(nir_shader *shader);
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bool pan_nir_lower_sample_pos(nir_shader *shader);
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bool pan_nir_lower_xfb(nir_shader *nir);
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117
src/panfrost/compiler/pan_nir_lower_varyings_io.c
Normal file
117
src/panfrost/compiler/pan_nir_lower_varyings_io.c
Normal file
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@ -0,0 +1,117 @@
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/*
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* Copyright (C) 2025 Collabora, Ltd.
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* SPDX-License-Identifier: MIT
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*/
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#include "pan_nir.h"
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#include "nir_builder.h"
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#include "panfrost/model/pan_model.h"
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struct lower_fs_inputs_ctx {
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unsigned arch;
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const struct pan_varying_layout *varying_layout;
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bool valhall_use_ld_var_buf;
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};
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static bool
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lower_fs_input_load(struct nir_builder *b,
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nir_intrinsic_instr *load, void *cb_data)
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{
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const struct lower_fs_inputs_ctx *ctx = cb_data;
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if (load->intrinsic != nir_intrinsic_load_input &&
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load->intrinsic != nir_intrinsic_load_interpolated_input)
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return false;
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const nir_io_semantics sem = nir_intrinsic_io_semantics(load);
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const nir_alu_type dest_type = nir_intrinsic_dest_type(load);
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/* Indirect array varyings are not yet supported (num_slots > 1) */
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assert(sem.num_slots == 1);
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assert(nir_src_as_uint(*nir_get_io_offset_src(load)) == 0);
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nir_intrinsic_instr *bary;
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switch (load->intrinsic) {
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case nir_intrinsic_load_input:
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bary = NULL;
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break;
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case nir_intrinsic_load_interpolated_input:
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/* Cannot interpolate ints */
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assert(nir_alu_type_get_base_type(dest_type) == nir_type_float);
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bary = nir_src_as_intrinsic(load->src[0]);
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break;
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default:
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UNREACHABLE("Already handled");
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}
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b->cursor = nir_before_instr(&load->instr);
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const unsigned component = nir_intrinsic_component(load);
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const unsigned load_comps = load->num_components + component;
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nir_def *res;
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if (ctx->valhall_use_ld_var_buf) {
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assert(ctx->arch >= 9);
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pan_varying_layout_require_layout(ctx->varying_layout);
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const struct pan_varying_slot *slot =
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pan_varying_layout_find_slot(ctx->varying_layout,
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sem.location);
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assert(slot);
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const nir_alu_type src_type = slot->alu_type;
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nir_def *offset_B = nir_imm_int(b, slot->offset);
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if (load->intrinsic == nir_intrinsic_load_interpolated_input) {
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res = nir_load_var_buf_pan(b, load_comps, load->def.bit_size,
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offset_B, &bary->def,
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.src_type = src_type,
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.io_semantics = sem);
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} else {
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res = nir_load_var_buf_flat_pan(b, load_comps, load->def.bit_size,
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offset_B,
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.src_type = src_type,
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.io_semantics = sem);
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}
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} else {
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const uint32_t base = nir_intrinsic_base(load);
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nir_def *idx = nir_imm_int(b, base);
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if (load->intrinsic == nir_intrinsic_load_interpolated_input) {
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res = nir_load_var_pan(b, load_comps, load->def.bit_size,
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idx, &bary->def,
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.dest_type = dest_type,
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.io_semantics = sem);
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} else {
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res = nir_load_var_flat_pan(b, load_comps, load->def.bit_size, idx,
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.dest_type = dest_type,
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.io_semantics = sem);
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}
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}
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if (component > 0) {
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unsigned swiz[NIR_MAX_VEC_COMPONENTS] = {0, };
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for (unsigned c = 0; c < load->num_components; c++)
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swiz[c] = component + c;
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res = nir_swizzle(b, res, swiz, load->num_components);
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}
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nir_def_replace(&load->def, res);
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return true;
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}
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bool
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pan_nir_lower_fs_inputs(nir_shader *shader, unsigned gpu_id,
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const struct pan_varying_layout *varying_layout,
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bool valhall_use_ld_var_buf)
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{
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const struct lower_fs_inputs_ctx ctx = {
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.arch = pan_arch(gpu_id),
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.varying_layout = varying_layout,
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.valhall_use_ld_var_buf = valhall_use_ld_var_buf,
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};
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return nir_shader_intrinsics_pass(shader, lower_fs_input_load,
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nir_metadata_control_flow,
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(void *)&ctx);
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}
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