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nir/opcodes: Avoid technical UB left shifting ints.
We all know that (int)0xff << 24 is fine, but UBSan doesn't like it. These were triggered by nir_opt_algebraic_pattern_tests. Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39076>
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1 changed files with 5 additions and 5 deletions
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@ -590,7 +590,7 @@ dst = -1;
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/* We are looking for the highest bit that's not the same as the sign bit. */
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uint32_t sign = src0 & 0x80000000u;
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for (int bit = 0; bit < 32; bit++) {
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if (((src0 << bit) & 0x80000000u) != sign) {
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if ((((uint32_t)src0 << bit) & 0x80000000u) != sign) {
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dst = bit;
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break;
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}
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@ -1228,7 +1228,7 @@ if (bits == 0) {
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dst = 0;
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poison = true;
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} else {
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dst = (base << (32 - offset - bits)) >> (32 - bits); /* use sign-extending shift */
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dst = (int32_t)((uint32_t)base << (32 - offset - bits)) >> (32 - bits); /* use sign-extending shift */
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}
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""")
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@ -1350,7 +1350,7 @@ binop("amul", tint, _2src_commutative + associative, "src0 * src1")
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# multiplication (imul) on Freedreno backend..
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opcode("imadsh_mix16", 0, tint32,
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[0, 0, 0], [tint32, tint32, tint32], False, "", """
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dst = ((((src0 & 0x0000ffff) << 16) * (src1 & 0xffff0000)) >> 16) + src2;
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dst = (((int32_t)(((uint32_t)src0 & 0x0000ffff) << 16) * (src1 & 0xffff0000)) >> 16) + src2;
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""")
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# ir3-specific instruction that maps directly to ir3 mad.s24.
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@ -1528,7 +1528,7 @@ opcode("lea_nv", 0, tuint, [0, 0, 0], [tuint, tuint, tuint32], False,
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# 24b multiply into 32b result (with sign extension)
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binop("imul24", tint32, _2src_commutative,
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"(((int32_t)src0 << 8) >> 8) * (((int32_t)src1 << 8) >> 8)")
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"util_mask_sign_extend(src0, 24) * util_mask_sign_extend(src1, 24)")
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# unsigned 24b multiply into 32b result plus 32b int
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triop("umad24", tuint32, _2src_commutative,
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@ -1574,7 +1574,7 @@ for (int i = 0; i < 32; i += 8) {
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int src0_chan = (src0 >> i) & 0xff;
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int src1_chan = (src1 >> i) & 0xff;
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if (src0_chan > src1_chan)
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dst |= (src0_chan - src1_chan) << i;
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dst |= (uint32_t)(src0_chan - src1_chan) << i;
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}
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""")
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