From 8500e9e1f01b71de1fee851ba0427b7ab13b8d94 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Fri, 24 Sep 2021 02:30:38 +0200 Subject: [PATCH] radv: Add DMA buffer update function for internal use. Only split out the DMA part because that doesn't need the BO. Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_meta.h | 3 +++ src/amd/vulkan/radv_meta_buffer.c | 40 ++++++++++++++++++------------- 2 files changed, 27 insertions(+), 16 deletions(-) diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h index 81ed74769c6..00d3311f9d0 100644 --- a/src/amd/vulkan/radv_meta.h +++ b/src/amd/vulkan/radv_meta.h @@ -249,6 +249,9 @@ uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *i uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value); +void radv_update_buffer_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const void *data, + uint64_t size); + /** * Return whether the bound pipeline is the FMASK decompress pass. */ diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index 39e805f932b..644558c50dc 100644 --- a/src/amd/vulkan/radv_meta_buffer.c +++ b/src/amd/vulkan/radv_meta_buffer.c @@ -414,14 +414,35 @@ radv_CmdCopyBuffer2KHR(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2KHR } } +void +radv_update_buffer_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const void *data, + uint64_t size) +{ + uint64_t words = size / 4; + bool mec = radv_cmd_buffer_uses_mec(cmd_buffer); + + assert(size < RADV_BUFFER_UPDATE_THRESHOLD); + + si_emit_cache_flush(cmd_buffer); + radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4); + + radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + words, 0)); + radeon_emit(cmd_buffer->cs, S_370_DST_SEL(mec ? V_370_MEM : V_370_MEM_GRBM) | + S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME)); + radeon_emit(cmd_buffer->cs, va); + radeon_emit(cmd_buffer->cs, va >> 32); + radeon_emit_array(cmd_buffer->cs, data, words); + + if (unlikely(cmd_buffer->device->trace_bo)) + radv_cmd_buffer_trace_emit(cmd_buffer); +} + void radv_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void *pData) { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer); - bool mec = radv_cmd_buffer_uses_mec(cmd_buffer); - uint64_t words = dataSize / 4; uint64_t va = radv_buffer_get_va(dst_buffer->bo); va += dstOffset + dst_buffer->offset; @@ -432,21 +453,8 @@ radv_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDevice return; if (dataSize < RADV_BUFFER_UPDATE_THRESHOLD) { - si_emit_cache_flush(cmd_buffer); - radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo); - - radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4); - - radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + words, 0)); - radeon_emit(cmd_buffer->cs, S_370_DST_SEL(mec ? V_370_MEM : V_370_MEM_GRBM) | - S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME)); - radeon_emit(cmd_buffer->cs, va); - radeon_emit(cmd_buffer->cs, va >> 32); - radeon_emit_array(cmd_buffer->cs, pData, words); - - if (unlikely(cmd_buffer->device->trace_bo)) - radv_cmd_buffer_trace_emit(cmd_buffer); + radv_update_buffer_cp(cmd_buffer, va, pData, dataSize); } else { uint32_t buf_offset; radv_cmd_buffer_upload_data(cmd_buffer, dataSize, pData, &buf_offset);