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nvk: Emit SET_CT_SELECT based on the dynamic color location map
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
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b1abf771c7
commit
84de6c12b2
1 changed files with 67 additions and 19 deletions
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@ -575,6 +575,9 @@ nvk_cmd_buffer_dirty_render_pass(struct nvk_cmd_buffer *cmd)
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/* This may depend on render targets for ESO */
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BITSET_SET(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES);
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/* This may depend on render targets */
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BITSET_SET(dyn->dirty, MESA_VK_DYNAMIC_COLOR_ATTACHMENT_MAP);
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}
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static void
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@ -804,9 +807,7 @@ nvk_CmdBeginRendering(VkCommandBuffer commandBuffer,
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nvk_cmd_buffer_dirty_render_pass(cmd);
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/* Always emit at least one color attachment, even if it's just a dummy. */
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uint32_t color_att_count = MAX2(1, render->color_att_count);
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struct nv_push *p = nvk_cmd_buffer_push(cmd, color_att_count * 12 + 29);
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struct nv_push *p = nvk_cmd_buffer_push(cmd, NVK_MAX_RTS * 12 + 29);
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P_IMMD(p, NV9097, SET_MME_SHADOW_SCRATCH(NVK_MME_SCRATCH_VIEW_MASK),
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render->view_mask);
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@ -822,7 +823,14 @@ nvk_CmdBeginRendering(VkCommandBuffer commandBuffer,
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});
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enum nil_sample_layout sample_layout = NIL_SAMPLE_LAYOUT_INVALID;
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for (uint32_t i = 0; i < color_att_count; i++) {
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/* We always emit SET_COLOR_TARGET_A(i) for every color target, regardless
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* of the number of targets in the render pass. This ensures that we have
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* no left over pointers from previous render passes in the hardware. This
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* also allows us to point at any render target with SET_CT_SELECT and know
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* that it's either a valid render target or NULL.
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*/
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for (uint32_t i = 0; i < NVK_MAX_RTS; i++) {
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if (render->color_att[i].iview) {
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const struct nvk_image_view *iview = render->color_att[i].iview;
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const struct nvk_image *image = (struct nvk_image *)iview->vk.image;
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@ -944,18 +952,6 @@ nvk_CmdBeginRendering(VkCommandBuffer commandBuffer,
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}
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}
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P_IMMD(p, NV9097, SET_CT_SELECT, {
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.target_count = color_att_count,
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.target0 = 0,
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.target1 = 1,
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.target2 = 2,
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.target3 = 3,
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.target4 = 4,
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.target5 = 5,
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.target6 = 6,
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.target7 = 7,
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});
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if (render->depth_att.iview || render->stencil_att.iview) {
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struct nvk_image_view *iview = render->depth_att.iview ?
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render->depth_att.iview :
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@ -2813,7 +2809,7 @@ nvk_flush_cb_state(struct nvk_cmd_buffer *cmd)
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&cmd->vk.dynamic_graphics_state;
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struct nv_push *p =
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nvk_cmd_buffer_push(cmd, 13 + 10 * render->color_att_count);
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nvk_cmd_buffer_push(cmd, 15 + 10 * render->color_att_count);
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if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE))
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P_IMMD(p, NV9097, SET_LOGIC_OP, dyn->cb.logic_op_enable);
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@ -2852,7 +2848,8 @@ nvk_flush_cb_state(struct nvk_cmd_buffer *cmd)
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if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_WRITE_MASKS) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RP_ATTACHMENTS)) {
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RP_ATTACHMENTS) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_COLOR_ATTACHMENT_MAP)) {
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uint32_t color_write_enables = 0x0;
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for (uint8_t a = 0; a < render->color_att_count; a++) {
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if (dyn->cb.color_write_enables & BITFIELD_BIT(a))
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@ -2869,11 +2866,62 @@ nvk_flush_cb_state(struct nvk_cmd_buffer *cmd)
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rp_att_write_mask |= 0xf << (4 * a);
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}
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uint32_t att_has_loc_mask = 0x0;
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for (uint8_t a = 0; a < MESA_VK_MAX_COLOR_ATTACHMENTS; a++) {
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if (dyn->cal.color_map[a] != MESA_VK_ATTACHMENT_UNUSED)
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att_has_loc_mask |= 0xf << (4 * a);
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}
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P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_SET_WRITE_MASK));
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P_INLINE_DATA(p, render->color_att_count);
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P_INLINE_DATA(p, color_write_enables &
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cb_att_write_mask &
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rp_att_write_mask);
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rp_att_write_mask &
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att_has_loc_mask);
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}
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if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_COLOR_ATTACHMENT_MAP)) {
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int8_t loc_att[NVK_MAX_RTS] = { -1, -1, -1, -1, -1, -1, -1, -1};
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uint8_t max_loc = 0;
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uint32_t att_used = 0;
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for (uint8_t a = 0; a < MESA_VK_MAX_COLOR_ATTACHMENTS; a++) {
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if (dyn->cal.color_map[a] == MESA_VK_ATTACHMENT_UNUSED)
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continue;
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att_used |= BITFIELD_BIT(a);
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assert(dyn->cal.color_map[a] < NVK_MAX_RTS);
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loc_att[dyn->cal.color_map[a]] = a;
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max_loc = MAX2(max_loc, dyn->cal.color_map[a]);
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}
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for (uint8_t l = 0; l < NVK_MAX_RTS; l++) {
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if (loc_att[l] >= 0)
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continue;
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/* Just grab any color attachment. The way we set up color targets
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* in BeginRenderPass ensures that every color target is either the
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* valid color target referenced by this render pass or a valid NULL
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* target. If we end up mapping to some other target in this render
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* pass, the handling of att_has_loc_mask above will ensure that no
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* color writes actually happen.
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*/
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uint8_t a = ffs(~att_used) - 1;
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att_used |= BITFIELD_BIT(a);
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loc_att[l] = a;
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}
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P_IMMD(p, NV9097, SET_CT_SELECT, {
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.target_count = max_loc + 1,
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.target0 = loc_att[0],
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.target1 = loc_att[1],
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.target2 = loc_att[2],
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.target3 = loc_att[3],
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.target4 = loc_att[4],
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.target5 = loc_att[5],
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.target6 = loc_att[6],
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.target7 = loc_att[7],
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});
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}
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if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_BLEND_CONSTANTS)) {
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