radeonsi: Support HEVC features and block sizes for UVD

Features are the same as VCN 1.0, block sizes are different.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31872>
This commit is contained in:
David Rosca 2024-09-30 15:28:57 +02:00 committed by Marge Bot
parent 4f31625aa6
commit 84bce1af41

View file

@ -718,9 +718,8 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 1 : 0;
case PIPE_VIDEO_CAP_ENC_HEVC_FEATURE_FLAGS:
if ((sscreen->info.vcn_ip_version >= VCN_1_0_0) &&
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) {
if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
union pipe_h265_enc_cap_features pipe_features;
pipe_features.value = 0;
@ -741,9 +740,8 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return 0;
case PIPE_VIDEO_CAP_ENC_HEVC_BLOCK_SIZES:
if (sscreen->info.vcn_ip_version >= VCN_1_0_0 &&
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) {
if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
union pipe_h265_enc_cap_block_sizes pipe_block_sizes;
pipe_block_sizes.value = 0;
@ -753,6 +751,13 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
pipe_block_sizes.bits.log2_max_luma_transform_block_size_minus2 = 3;
pipe_block_sizes.bits.log2_min_luma_transform_block_size_minus2 = 0;
if (sscreen->info.ip[AMD_IP_UVD_ENC].num_queues) {
pipe_block_sizes.bits.max_max_transform_hierarchy_depth_inter = 3;
pipe_block_sizes.bits.min_max_transform_hierarchy_depth_inter = 3;
pipe_block_sizes.bits.max_max_transform_hierarchy_depth_intra = 3;
pipe_block_sizes.bits.min_max_transform_hierarchy_depth_intra = 3;
}
return pipe_block_sizes.value;
} else
return 0;