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pvr: Feature support TPU_PARALLEL_INSTANCES
Signed-off-by: Ashish Chauhan <Ashish.Chauhan@imgtec.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
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6 changed files with 23 additions and 11 deletions
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@ -59,6 +59,7 @@ static const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.has_tpu_border_colour_enhanced = true,
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.has_tpu_extended_integer_lookup = true,
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.has_tpu_image_state_v2 = true,
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.has_tpu_parallel_instances = true,
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.has_unified_store_depth = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_min_output_registers_per_pix = true,
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@ -83,6 +84,7 @@ static const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.slc_cache_line_size_bits = 512U,
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.tile_size_x = 16U,
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.tile_size_y = 16U,
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.tpu_parallel_instances = 1U,
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.unified_store_depth = 64U,
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.usc_min_output_registers_per_pix = 1U,
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.usc_slots = 14U,
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@ -66,6 +66,7 @@ static const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.has_tpu_dm_global_registers = true,
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.has_tpu_extended_integer_lookup = true,
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.has_tpu_image_state_v2 = true,
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.has_tpu_parallel_instances = true,
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.has_unified_store_depth = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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@ -94,6 +95,7 @@ static const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.slc_cache_line_size_bits = 512U,
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.tile_size_x = 16U,
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.tile_size_y = 16U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 256U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 64U,
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@ -59,6 +59,7 @@ static const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.has_tpu_array_textures = true,
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.has_tpu_extended_integer_lookup = true,
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.has_tpu_image_state_v2 = true,
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.has_tpu_parallel_instances = true,
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.has_unified_store_depth = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_itrsmp = true,
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@ -84,6 +85,7 @@ static const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.slc_cache_line_size_bits = 512U,
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.tile_size_x = 32U,
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.tile_size_y = 32U,
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.tpu_parallel_instances = 4U,
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.unified_store_depth = 256U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 32U,
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@ -291,6 +291,7 @@ struct pvr_device_features {
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bool has_tpu_dm_global_registers : 1;
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bool has_tpu_extended_integer_lookup : 1;
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bool has_tpu_image_state_v2 : 1;
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bool has_tpu_parallel_instances : 1;
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bool has_unified_store_depth : 1;
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bool has_usc_f16sop_u8 : 1;
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bool has_usc_itrsmp : 1;
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@ -321,6 +322,7 @@ struct pvr_device_features {
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uint32_t slc_cache_line_size_bits;
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uint32_t tile_size_x;
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uint32_t tile_size_y;
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uint32_t tpu_parallel_instances;
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uint32_t unified_store_depth;
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uint32_t usc_min_output_registers_per_pix;
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uint32_t usc_slots;
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@ -267,12 +267,23 @@ rogue_get_slc_cache_line_size(const struct pvr_device_info *dev_info)
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static inline uint32_t pvr_get_max_user_vertex_output_components(
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const struct pvr_device_info *dev_info)
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{
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/* Default value based on the minimum value found in all existing cores. */
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const uint32_t uvs_pba_entries =
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PVR_GET_FEATURE_VALUE(dev_info, uvs_pba_entries, 0U);
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const uint32_t uvs_banks = PVR_GET_FEATURE_VALUE(dev_info, uvs_banks, 0U);
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PVR_GET_FEATURE_VALUE(dev_info, uvs_pba_entries, 160U);
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/* Default value based on the minimum value found in all existing cores. */
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const uint32_t uvs_banks = PVR_GET_FEATURE_VALUE(dev_info, uvs_banks, 2U);
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if (uvs_banks <= 8U && uvs_pba_entries == 160U) {
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ASSERTED const uint32_t tpu_parallel_instances =
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PVR_GET_FEATURE_VALUE(dev_info, tpu_parallel_instances, 1U);
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/* Cores with > 2 ppc support vertex sizes of >= 128 dwords */
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assert(tpu_parallel_instances <= 2 ||
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(dev_info->ident.b <= 36 || dev_info->ident.b == 46));
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if (uvs_banks <= 8U && uvs_pba_entries == 160U)
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return 64U;
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}
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return 128U;
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}
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@ -308,13 +308,6 @@ static bool pvr_physical_device_get_properties(
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const uint32_t max_multisample =
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PVR_GET_FEATURE_VALUE(dev_info, max_multisample, 4);
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/* Default value based on the minimum value found in all existing cores. */
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const uint32_t uvs_banks = PVR_GET_FEATURE_VALUE(dev_info, uvs_banks, 2);
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/* Default value based on the minimum value found in all existing cores. */
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const uint32_t uvs_pba_entries =
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PVR_GET_FEATURE_VALUE(dev_info, uvs_pba_entries, 160);
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UNUSED const uint32_t sub_pixel_precision =
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PVR_HAS_FEATURE(dev_info, simple_internal_parameter_format) ? 4U : 8U;
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@ -323,7 +316,7 @@ static bool pvr_physical_device_get_properties(
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UNUSED const uint32_t max_sample_bits = ((max_multisample << 1) - 1);
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UNUSED const uint32_t max_user_vertex_components =
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((uvs_banks <= 8U) && (uvs_pba_entries == 160U)) ? 64U : 128U;
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pvr_get_max_user_vertex_output_components(dev_info);
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/* The workgroup invocations are limited by the case where we have a compute
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* barrier - each slot has a fixed number of invocations, the whole workgroup
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