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anv: Handle bits to flush data-port's Untyped L1 data cache

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v2: Drop ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT from invalidate bits (Lionel)
    Add utrace support
    Expand on comment about PIPE_CONTROL::UntypedDataPortCache

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
This commit is contained in:
Sagar Ghuge 2021-08-11 16:53:42 -07:00 • committed by Lionel Landwerlin
parent 1f34ce7e8e
commit 845ab3d627
4 changed files with 48 additions and 3 deletions
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14
src/intel/vulkan/anv_private.h
View file

@ -2238,6 +2238,12 @@ enum anv_pipe_bits {
*/
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT = (1 << 14),
ANV_PIPE_PSS_STALL_SYNC_BIT = (1 << 15),
/*
* This bit flush data-port's Untyped L1 data cache (LSC L1).
*/
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT = (1 << 16),
ANV_PIPE_CS_STALL_BIT = (1 << 20),
ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),
@ -2273,6 +2279,7 @@ enum anv_pipe_bits {
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | \
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT | \
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
ANV_PIPE_TILE_CACHE_FLUSH_BIT)
@ -2308,6 +2315,7 @@ anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
* to future operations, flush the hdc pipeline.
*/
pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT:
/* We're transitioning a buffer that was previously used as render
@ -2415,10 +2423,12 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
* port) to avoid stale data.
*/
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
if (device->physical->compiler->indirect_ubos_use_sampler)
if (device->physical->compiler->indirect_ubos_use_sampler) {
pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
else
} else {
pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
}
break;
case VK_ACCESS_2_SHADER_READ_BIT:
case VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT:

2
src/intel/vulkan/anv_util.c
View file

@ -87,4 +87,6 @@ anv_dump_pipe_bits(enum anv_pipe_bits bits)
fputs("+depth_stall ", stderr);
if (bits & ANV_PIPE_CS_STALL_BIT)
fputs("+cs_stall ", stderr);
if (bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT)
fputs("+utdp_flush", stderr);
}

1
src/intel/vulkan/anv_utrace.c
View file

@ -333,6 +333,7 @@ anv_pipe_flush_bit_to_ds_stall_flag(enum anv_pipe_bits bits)
{ .anv = ANV_PIPE_CS_STALL_BIT, .ds = INTEL_DS_CS_STALL_BIT, },
{ .anv = ANV_PIPE_HDC_PIPELINE_FLUSH_BIT, .ds = INTEL_DS_HDC_PIPELINE_FLUSH_BIT, },
{ .anv = ANV_PIPE_STALL_AT_SCOREBOARD_BIT, .ds = INTEL_DS_STALL_AT_SCOREBOARD_BIT, },
{ .anv = ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT, .ds = INTEL_DS_UNTYPED_DATAPORT_CACHE_FLUSH_BIT, },
};
enum intel_ds_stall_flag ret = 0;

34
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -77,6 +77,9 @@ convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
bits |= (pc->StallAtPixelScoreboard) ? ANV_PIPE_STALL_AT_SCOREBOARD_BIT : 0;
bits |= (pc->DepthStallEnable) ? ANV_PIPE_DEPTH_STALL_BIT : 0;
bits |= (pc->CommandStreamerStallEnable) ? ANV_PIPE_CS_STALL_BIT : 0;
#if GFX_VERx10 == 125
bits |= (pc->UntypedDataPortCacheFlushEnable) ? ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT : 0;
#endif
return bits;
}
@ -2085,6 +2088,34 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS |
ANV_PIPE_END_OF_PIPE_SYNC_BIT)) {
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
#if GFX_VERx10 >= 125
/* BSpec 47112: PIPE_CONTROL::Untyped Data-Port Cache Flush:
*
* "'HDC Pipeline Flush' bit must be set for this bit to take
* effect."
*
* BSpec 47112: PIPE_CONTROL::HDC Pipeline Flush:
*
* "When the "Pipeline Select" mode in PIPELINE_SELECT command is
* set to "3D", HDC Pipeline Flush can also flush/invalidate the
* LSC Untyped L1 cache based on the programming of HDC_Chicken0
* register bits 13:11."
*
* "When the 'Pipeline Select' mode is set to 'GPGPU', the LSC
* Untyped L1 cache flush is controlled by 'Untyped Data-Port
* Cache Flush' bit in the PIPE_CONTROL command."
*
* As part of Wa_1608949956 & Wa_14010198302, i915 is programming
* HDC_CHICKEN0[11:13] = 0 ("Untyped L1 is flushed, for both 3D
* Pipecontrol Dataport flush, and UAV coherency barrier event").
* So there is no need to set "Untyped Data-Port Cache" in 3D
* mode.
*/
pipe.UntypedDataPortCacheFlushEnable =
(bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT) &&
current_pipeline == GPGPU;
pipe.HDCPipelineFlushEnable |= pipe.UntypedDataPortCacheFlushEnable;
#endif
#if GFX_VER >= 12
pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
pipe.HDCPipelineFlushEnable |= bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
@ -5920,7 +5951,8 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT,
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT,
"flush and invalidate for PIPELINE_SELECT");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);