From 8452bd798425d9e5577a998ca89dd4943a92b064 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 19 May 2022 19:18:29 +0200 Subject: [PATCH] etnaviv: improve single buffer setup The blob only switches to the 3 single buffer state when required, which seems to be the case when any color or ZS target is <= 16bpp. Using 2 as the single buffer state gives a very small 1-2% performance improvement on fillrate constrained rendering, so it likely affects some PE cache setting. Signed-off-by: Lucas Stach Reviewed-by: Christian Gmeiner Part-of: --- src/gallium/drivers/etnaviv/etnaviv_state.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c b/src/gallium/drivers/etnaviv/etnaviv_state.c index ffc9b741368..6b2f9bcdd17 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_state.c +++ b/src/gallium/drivers/etnaviv/etnaviv_state.c @@ -135,6 +135,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx, struct compiled_framebuffer_state *cs = &ctx->framebuffer; int nr_samples_color = -1; int nr_samples_depth = -1; + bool target_16bpp = false; /* Set up TS as well. Warning: this state is used by both the RS and PE */ uint32_t ts_mem_config = 0; @@ -156,6 +157,9 @@ etna_set_framebuffer_state(struct pipe_context *pctx, else cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt); + if (util_format_get_blocksize(cbuf->base.format) <= 2) + target_16bpp = true; + cs->PE_COLOR_FORMAT |= VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK | VIVS_PE_COLOR_FORMAT_OVERWRITE | @@ -251,6 +255,9 @@ etna_set_framebuffer_state(struct pipe_context *pctx, depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24; bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0; + if (depth_bits == 16) + target_16bpp = true; + cs->PE_DEPTH_CONFIG = depth_format | COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) | @@ -358,9 +365,9 @@ etna_set_framebuffer_state(struct pipe_context *pctx, /* Single buffer setup. There is only one switch for this, not a separate * one per color buffer / depth buffer. To keep the logic simple always use * single buffer when this feature is available. - * note: the blob will use 2 in some situations, figure out why? */ - pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(screen->specs.single_buffer ? 3 : 0); + if (screen->specs.single_buffer) + pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(target_16bpp ? 3 : 2); cs->PE_LOGIC_OP = pe_logic_op; /* keep copy of original structure */