From 8426cf9132a6466bd4e4dbd27cc7003578ad9fd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 11 Jul 2022 00:38:43 -0400 Subject: [PATCH] ac/gpu_info: remove unused has_unaligned_shader_loads Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_gpu_info.c | 3 --- src/amd/common/ac_gpu_info.h | 1 - src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 3 --- 3 files changed, 7 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 63e0cd084be..228e2de5a3a 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -967,8 +967,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info) info->si_TA_CS_BC_BASE_ADDR_allowed = true; info->has_bo_metadata = true; info->has_eqaa_surface_allocator = info->gfx_level < GFX11; - /* GFX6 doesn't support unaligned loads. */ - info->has_unaligned_shader_loads = info->gfx_level != GFX6; /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once * these faults are mitigated in software. */ @@ -1570,7 +1568,6 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed); fprintf(f, " has_bo_metadata = %u\n", info->has_bo_metadata); fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator); - fprintf(f, " has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads); fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings); fprintf(f, " has_stable_pstate = %u\n", info->has_stable_pstate); fprintf(f, " has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index cbbf186a11a..a40b3e4d208 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -186,7 +186,6 @@ struct radeon_info { bool si_TA_CS_BC_BASE_ADDR_allowed; bool has_bo_metadata; bool has_eqaa_surface_allocator; - bool has_unaligned_shader_loads; bool has_sparse_vm_mappings; bool has_scheduled_fence_dependency; bool has_stable_pstate; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 3f3a3aa410c..7511a597462 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -573,9 +573,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48; ws->info.has_bo_metadata = false; ws->info.has_eqaa_surface_allocator = false; - /* GFX6 doesn't support unaligned loads. */ - ws->info.has_unaligned_shader_loads = ws->info.gfx_level == GFX7 && - ws->info.drm_minor >= 50; ws->info.has_sparse_vm_mappings = false; ws->info.max_alignment = 1024*1024; ws->info.has_graphics = true;