fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 11:18:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965: Validate "General Restrictions on Regioning Parameters"

Browse source
This commit is contained in:
Matt Turner 2016-11-05 20:49:48 -07:00
parent df0b7bcdfd
commit 83696b2234
2 changed files with 377 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

157
src/mesa/drivers/dri/i965/brw_eu_validate.c
View file

@ -63,6 +63,13 @@ cat(struct string *dest, const struct string src)
} \
} while (0)
static bool
dst_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_dst_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
brw_inst_dst_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
}
static bool
src0_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
{
@ -187,6 +194,155 @@ is_unsupported_inst(const struct gen_device_info *devinfo,
return brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst)) == NULL;
}
/**
* Checks restrictions listed in "General Restrictions on Regioning Parameters"
* in the "Register Region Restrictions" section.
*/
static struct string
general_restrictions_on_region_parameters(const struct gen_device_info *devinfo,
const brw_inst *inst)
{
const struct opcode_desc *desc =
brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst));
unsigned num_sources = num_sources_from_inst(devinfo, inst);
unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst);
struct string error_msg = { .str = NULL, .len = 0 };
if (num_sources == 3)
return (struct string){};
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16) {
if (desc->ndst != 0 && !dst_is_null(devinfo, inst))
ERROR_IF(brw_inst_dst_hstride(devinfo, inst) != BRW_HORIZONTAL_STRIDE_1,
"Destination Horizontal Stride must be 1");
if (num_sources >= 1) {
if (devinfo->is_haswell || devinfo->gen >= 8) {
ERROR_IF(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4,
"In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
} else {
ERROR_IF(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4,
"In Align16 mode, only VertStride of 0 or 4 is allowed");
}
}
if (num_sources == 2) {
if (devinfo->is_haswell || devinfo->gen >= 8) {
ERROR_IF(brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4,
"In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
} else {
ERROR_IF(brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4,
"In Align16 mode, only VertStride of 0 or 4 is allowed");
}
}
return error_msg;
}
for (unsigned i = 0; i < num_sources; i++) {
unsigned vstride, width, hstride, element_size, subreg;
#define DO_SRC(n) \
if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
BRW_IMMEDIATE_VALUE) \
continue; \
\
vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
(1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
(1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
element_size = brw_element_size(devinfo, inst, src ## n); \
subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
if (i == 0) {
DO_SRC(0);
} else if (i == 1) {
DO_SRC(1);
}
#undef DO_SRC
/* ExecSize must be greater than or equal to Width. */
ERROR_IF(exec_size < width, "ExecSize must be greater than or equal "
"to Width");
/* If ExecSize = Width and HorzStride ≠ 0,
* VertStride must be set to Width * HorzStride.
*/
if (exec_size == width && hstride != 0) {
ERROR_IF(vstride != width * hstride,
"If ExecSize = Width and HorzStride ≠ 0, "
"VertStride must be set to Width * HorzStride");
}
/* If Width = 1, HorzStride must be 0 regardless of the values of
* ExecSize and VertStride.
*/
if (width == 1) {
ERROR_IF(hstride != 0,
"If Width = 1, HorzStride must be 0 regardless "
"of the values of ExecSize and VertStride");
}
/* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
if (exec_size == 1 && width == 1) {
ERROR_IF(vstride != 0 || hstride != 0,
"If ExecSize = Width = 1, both VertStride "
"and HorzStride must be 0");
}
/* If VertStride = HorzStride = 0, Width must be 1 regardless of the
* value of ExecSize.
*/
if (vstride == 0 && hstride == 0) {
ERROR_IF(width != 1,
"If VertStride = HorzStride = 0, Width must be "
"1 regardless of the value of ExecSize");
}
/* VertStride must be used to cross GRF register boundaries. This rule
* implies that elements within a 'Width' cannot cross GRF boundaries.
*/
const uint64_t mask = (1 << element_size) - 1;
unsigned rowbase = subreg;
for (int y = 0; y < exec_size / width; y++) {
uint64_t access_mask = 0;
unsigned offset = rowbase;
for (int x = 0; x < width; x++) {
access_mask |= mask << offset;
offset += hstride * element_size;
}
rowbase += vstride * element_size;
if ((uint32_t)access_mask != 0 && (access_mask >> 32) != 0) {
ERROR("VertStride must be used to cross GRF register boundaries");
break;
}
}
}
/* Dst.HorzStride must not be 0. */
if (desc->ndst != 0 && !dst_is_null(devinfo, inst)) {
ERROR_IF(brw_inst_dst_hstride(devinfo, inst) == BRW_HORIZONTAL_STRIDE_0,
"Destination Horizontal Stride must not be 0");
}
return error_msg;
}
bool
brw_validate_instructions(const struct brw_codegen *p, int start_offset,
struct annotation_info *annotation)
@ -205,6 +361,7 @@ brw_validate_instructions(const struct brw_codegen *p, int start_offset,
} else {
CHECK(sources_not_null);
CHECK(send_restrictions);
CHECK(general_restrictions_on_region_parameters);
}
if (error_msg.str && annotation) {

220
src/mesa/drivers/dri/i965/test_eu_validate.cpp
View file

@ -128,9 +128,17 @@ validate(struct brw_codegen *p)
return ret;
}
#define last_inst (&p->store[p->nr_insn - 1])
#define g0 brw_vec8_grf(0, 0)
#define null brw_null_reg()
static void
clear_instructions(struct brw_codegen *p)
{
p->next_insn_offset = 0;
p->nr_insn = 0;
}
TEST_P(validation_test, sanity)
{
brw_ADD(p, g0, g0, g0);
@ -190,3 +198,215 @@ TEST_P(validation_test, opcode46)
EXPECT_TRUE(validate(p));
}
}
/* ExecSize must be greater than or equal to Width. */
TEST_P(validation_test, exec_size_less_than_width)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_16);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_16);
EXPECT_FALSE(validate(p));
}
/* If ExecSize = Width and HorzStride ≠ 0,
* VertStride must be set to Width * HorzStride.
*/
TEST_P(validation_test, vertical_stride_is_width_by_horizontal_stride)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
EXPECT_FALSE(validate(p));
}
/* If Width = 1, HorzStride must be 0 regardless of the values
* of ExecSize and VertStride.
*/
TEST_P(validation_test, horizontal_stride_must_be_0_if_width_is_1)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
EXPECT_FALSE(validate(p));
}
/* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
TEST_P(validation_test, scalar_region_must_be_0_1_0)
{
struct brw_reg g0_0 = brw_vec1_grf(0, 0);
brw_ADD(p, g0, g0, g0_0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_1);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_1);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0_0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_1);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_1);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
EXPECT_FALSE(validate(p));
}
/* If VertStride = HorzStride = 0, Width must be 1 regardless of the value
* of ExecSize.
*/
TEST_P(validation_test, zero_stride_implies_0_1_0)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
EXPECT_FALSE(validate(p));
}
/* Dst.HorzStride must not be 0. */
TEST_P(validation_test, dst_horizontal_stride_0)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
EXPECT_FALSE(validate(p));
}
/* VertStride must be used to cross GRF register boundaries. This rule implies
* that elements within a 'Width' cannot cross GRF boundaries.
*/
TEST_P(validation_test, must_not_cross_grf_boundary_in_a_width)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 4);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 4);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
EXPECT_FALSE(validate(p));
}
/* Destination Horizontal must be 1 in Align16 */
TEST_P(validation_test, dst_hstride_on_align16_must_be_1)
{
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
EXPECT_TRUE(validate(p));
}
/* VertStride must be 0 or 4 in Align16 */
TEST_P(validation_test, vstride_on_align16_must_be_0_or_4)
{
const struct {
enum brw_vertical_stride vstride;
bool expected_result;
} vstride[] = {
{ BRW_VERTICAL_STRIDE_0, true },
{ BRW_VERTICAL_STRIDE_1, false },
{ BRW_VERTICAL_STRIDE_2, devinfo.is_haswell || devinfo.gen >= 8 },
{ BRW_VERTICAL_STRIDE_4, true },
{ BRW_VERTICAL_STRIDE_8, false },
{ BRW_VERTICAL_STRIDE_16, false },
{ BRW_VERTICAL_STRIDE_32, false },
{ BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, false },
};
brw_set_default_access_mode(p, BRW_ALIGN_16);
for (unsigned i = 0; i < sizeof(vstride) / sizeof(vstride[0]); i++) {
brw_ADD(p, g0, g0, g0);
brw_inst_set_src0_vstride(&devinfo, last_inst, vstride[i].vstride);
EXPECT_EQ(vstride[i].expected_result, validate(p));
clear_instructions(p);
}
for (unsigned i = 0; i < sizeof(vstride) / sizeof(vstride[0]); i++) {
brw_ADD(p, g0, g0, g0);
brw_inst_set_src1_vstride(&devinfo, last_inst, vstride[i].vstride);
EXPECT_EQ(vstride[i].expected_result, validate(p));
clear_instructions(p);
}
}