mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-09 08:58:02 +02:00
radeon: derive radeon_renderbuffer from swrast_renderbuffer
(cherry picked from commit c080202db5)
This commit is contained in:
parent
b31bfae0db
commit
83602e8342
14 changed files with 73 additions and 64 deletions
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@ -1619,8 +1619,8 @@ void r200_vtbl_update_scissor( struct gl_context *ctx )
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rrb = radeon_get_colorbuffer(&r200->radeon);
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x1 = 0;
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y1 = 0;
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x2 = rrb->base.Width - 1;
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y2 = rrb->base.Height - 1;
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x2 = rrb->base.Base.Width - 1;
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y2 = rrb->base.Base.Height - 1;
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}
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R200_SET_STATE(r200, sci, SCI_XY_1, x1 | (y1 << 16));
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@ -451,7 +451,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
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atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
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if (rrb->cpp == 4)
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atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
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else switch (rrb->base.Format) {
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else switch (rrb->base.Base.Format) {
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case MESA_FORMAT_RGB565:
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atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
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break;
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@ -807,13 +807,14 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format
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}
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_mesa_init_teximage_fields(radeon->glCtx, texImage,
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rb->base.Width, rb->base.Height, 1, 0,
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rb->base.Base.Width, rb->base.Base.Height,
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1, 0,
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rb->cpp, texFormat);
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rImage->base.RowStride = rb->pitch / rb->cpp;
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t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
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| ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
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t->pp_txsize = ((rb->base.Base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
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| ((rb->base.Base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
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if (target == GL_TEXTURE_RECTANGLE_NV) {
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t->pp_txformat |= R200_TXFORMAT_NON_POWER2;
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@ -364,8 +364,8 @@ void radeon_draw_buffer(struct gl_context *ctx, struct gl_framebuffer *fb)
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ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);
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}
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_mesa_reference_renderbuffer(&radeon->state.depth.rb, &rrbDepth->base);
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_mesa_reference_renderbuffer(&radeon->state.color.rb, &rrbColor->base);
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_mesa_reference_renderbuffer(&radeon->state.depth.rb, &rrbDepth->base.Base);
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_mesa_reference_renderbuffer(&radeon->state.color.rb, &rrbColor->base.Base);
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radeon->state.color.draw_offset = offset;
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#if 0
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@ -45,7 +45,7 @@ static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbu
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radeon_print(RADEON_MEMORY, RADEON_TRACE,
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"%s(rb %p)\n",
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__func__, (void *) rb);
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if (rrb && rrb->base.ClassID == RADEON_RB_CLASS)
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if (rrb && rrb->base.Base.ClassID == RADEON_RB_CLASS)
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return rrb;
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else
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return NULL;
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@ -294,7 +294,7 @@ GLboolean radeonUnbindContext(__DRIcontext * driContextPriv)
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static unsigned
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radeon_bits_per_pixel(const struct radeon_renderbuffer *rb)
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{
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return _mesa_get_format_bytes(rb->base.Format) * 8;
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return _mesa_get_format_bytes(rb->base.Base.Format) * 8;
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}
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/*
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@ -484,8 +484,8 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
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rb->cpp = buffers[i].cpp;
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rb->pitch = buffers[i].pitch;
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rb->base.Width = drawable->w;
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rb->base.Height = drawable->h;
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rb->base.Base.Width = drawable->w;
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rb->base.Base.Height = drawable->h;
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rb->has_surface = 0;
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if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
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@ -602,9 +602,9 @@ GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
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if (driDrawPriv != driReadPriv)
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radeon_update_renderbuffers(driContextPriv, driReadPriv, GL_FALSE);
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_mesa_reference_renderbuffer(&radeon->state.color.rb,
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&(radeon_get_renderbuffer(drfb, BUFFER_BACK_LEFT)->base));
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&(radeon_get_renderbuffer(drfb, BUFFER_BACK_LEFT)->base.Base));
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_mesa_reference_renderbuffer(&radeon->state.depth.rb,
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&(radeon_get_renderbuffer(drfb, BUFFER_DEPTH)->base));
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&(radeon_get_renderbuffer(drfb, BUFFER_DEPTH)->base.Base));
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if (RADEON_DEBUG & RADEON_DRI)
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fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
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@ -80,7 +80,8 @@ typedef struct radeon_context *radeonContextPtr;
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struct radeon_renderbuffer
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{
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struct gl_renderbuffer base;
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struct swrast_renderbuffer base;
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struct radeon_bo *bo;
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unsigned int cpp;
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/* unsigned int offset; */
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@ -263,7 +263,7 @@ radeon_map_renderbuffer(struct gl_context *ctx,
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src_y = y;
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} else {
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src_x = x;
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src_y = rrb->base.Height - y - h;
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src_y = rrb->base.Base.Height - y - h;
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}
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/* Make a temporary buffer and blit the current contents of the renderbuffer
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@ -645,7 +645,7 @@ radeon_resize_buffers(struct gl_context *ctx, struct gl_framebuffer *fb,
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/* Make sure all window system renderbuffers are up to date */
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for (i = 0; i < 2; i++) {
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struct gl_renderbuffer *rb = &radeon_fb->color_rb[i]->base;
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struct gl_renderbuffer *rb = &radeon_fb->color_rb[i]->base.Base;
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/* only resize if size is changing */
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if (rb && (rb->Width != width || rb->Height != height)) {
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@ -673,6 +673,7 @@ struct radeon_renderbuffer *
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radeon_create_renderbuffer(gl_format format, __DRIdrawable *driDrawPriv)
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{
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struct radeon_renderbuffer *rrb;
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struct gl_renderbuffer *rb;
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rrb = CALLOC_STRUCT(radeon_renderbuffer);
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@ -683,18 +684,18 @@ radeon_create_renderbuffer(gl_format format, __DRIdrawable *driDrawPriv)
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if (!rrb)
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return NULL;
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_mesa_init_renderbuffer(&rrb->base, 0);
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rrb->base.ClassID = RADEON_RB_CLASS;
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rb = &rrb->base.Base;
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rrb->base.Format = format;
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rrb->base._BaseFormat = _mesa_get_format_base_format(format);
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_mesa_init_renderbuffer(rb, 0);
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rb->ClassID = RADEON_RB_CLASS;
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rb->Format = format;
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rb->_BaseFormat = _mesa_get_format_base_format(format);
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rb->InternalFormat = _mesa_get_format_base_format(format);
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rrb->dPriv = driDrawPriv;
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rrb->base.InternalFormat = _mesa_get_format_base_format(format);
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rrb->base.Delete = radeon_delete_renderbuffer;
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rrb->base.AllocStorage = radeon_alloc_window_storage;
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rb->Delete = radeon_delete_renderbuffer;
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rb->AllocStorage = radeon_alloc_window_storage;
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rrb->bo = NULL;
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return rrb;
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@ -704,6 +705,8 @@ static struct gl_renderbuffer *
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radeon_new_renderbuffer(struct gl_context * ctx, GLuint name)
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{
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struct radeon_renderbuffer *rrb;
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struct gl_renderbuffer *rb;
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rrb = CALLOC_STRUCT(radeon_renderbuffer);
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@ -714,13 +717,14 @@ radeon_new_renderbuffer(struct gl_context * ctx, GLuint name)
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if (!rrb)
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return NULL;
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_mesa_init_renderbuffer(&rrb->base, name);
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rrb->base.ClassID = RADEON_RB_CLASS;
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rb = &rrb->base.Base;
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rrb->base.Delete = radeon_delete_renderbuffer;
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rrb->base.AllocStorage = radeon_alloc_renderbuffer_storage;
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_mesa_init_renderbuffer(rb, name);
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rb->ClassID = RADEON_RB_CLASS;
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rb->Delete = radeon_delete_renderbuffer;
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rb->AllocStorage = radeon_alloc_renderbuffer_storage;
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return &rrb->base;
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return rb;
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}
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static void
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@ -761,19 +765,21 @@ static GLboolean
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radeon_update_wrapper(struct gl_context *ctx, struct radeon_renderbuffer *rrb,
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struct gl_texture_image *texImage)
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{
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struct gl_renderbuffer *rb = &rrb->base.Base;
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radeon_print(RADEON_TEXTURE, RADEON_TRACE,
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"%s(%p, rrb %p, texImage %p, texFormat %s) \n",
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__func__, ctx, rrb, texImage, _mesa_get_format_name(texImage->TexFormat));
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rrb->cpp = _mesa_get_format_bytes(texImage->TexFormat);
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rrb->pitch = texImage->Width * rrb->cpp;
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rrb->base.Format = texImage->TexFormat;
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rrb->base.InternalFormat = texImage->InternalFormat;
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rrb->base._BaseFormat = _mesa_base_fbo_format(ctx, rrb->base.InternalFormat);
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rrb->base.Width = texImage->Width;
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rrb->base.Height = texImage->Height;
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rrb->base.Delete = radeon_delete_renderbuffer;
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rrb->base.AllocStorage = radeon_nop_alloc_storage;
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rb->Format = texImage->TexFormat;
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rb->InternalFormat = texImage->InternalFormat;
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rb->_BaseFormat = _mesa_base_fbo_format(ctx, rb->InternalFormat);
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rb->Width = texImage->Width;
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rb->Height = texImage->Height;
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rb->Delete = radeon_delete_renderbuffer;
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rb->AllocStorage = radeon_nop_alloc_storage;
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return GL_TRUE;
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}
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@ -797,8 +803,8 @@ radeon_wrap_texture(struct gl_context * ctx, struct gl_texture_image *texImage)
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return NULL;
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}
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_mesa_init_renderbuffer(&rrb->base, name);
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rrb->base.ClassID = RADEON_RB_CLASS;
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_mesa_init_renderbuffer(&rrb->base.Base, name);
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rrb->base.Base.ClassID = RADEON_RB_CLASS;
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if (!radeon_update_wrapper(ctx, rrb, texImage)) {
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free(rrb);
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@ -840,7 +846,7 @@ radeon_render_texture(struct gl_context * ctx,
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rrb = radeon_wrap_texture(ctx, newImage);
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if (rrb) {
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/* bind the wrapper to the attachment point */
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_mesa_reference_renderbuffer(&att->Renderbuffer, &rrb->base);
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_mesa_reference_renderbuffer(&att->Renderbuffer, &rrb->base.Base);
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}
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else {
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/* fallback to software rendering */
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@ -858,7 +864,7 @@ radeon_render_texture(struct gl_context * ctx,
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DBG("Begin render texture tid %lx tex=%u w=%d h=%d refcount=%d\n",
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_glthread_GetID(),
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att->Texture->Name, newImage->Width, newImage->Height,
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rrb->base.RefCount);
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rrb->base.Base.RefCount);
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/* point the renderbufer's region to the texture image region */
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if (rrb->bo != radeon_image->mt->bo) {
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@ -150,17 +150,17 @@ do_blit_readpixels(struct gl_context * ctx,
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/* Disable source Y flipping for FBOs */
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flip_y = (ctx->ReadBuffer->Name == 0);
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if (pack->Invert) {
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y = rrb->base.Height - height - y;
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y = rrb->base.Base.Height - height - y;
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flip_y = !flip_y;
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}
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if (radeon->vtbl.blit(ctx,
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rrb->bo,
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rrb->draw_offset,
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rrb->base.Format,
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rrb->base.Base.Format,
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rrb->pitch / rrb->cpp,
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rrb->base.Width,
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rrb->base.Height,
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rrb->base.Base.Width,
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rrb->base.Base.Height,
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x,
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y,
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dst_buffer,
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@ -620,13 +620,13 @@ radeonCreateBuffer( __DRIscreen *driScrnPriv,
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/* front color renderbuffer */
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rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base.Base);
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rfb->color_rb[0]->has_surface = 1;
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/* back color renderbuffer */
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if (mesaVis->doubleBufferMode) {
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rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base.Base);
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rfb->color_rb[1]->has_surface = 1;
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}
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@ -634,21 +634,21 @@ radeonCreateBuffer( __DRIscreen *driScrnPriv,
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if (mesaVis->stencilBits == 8) {
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struct radeon_renderbuffer *depthStencilRb =
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radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base.Base);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base.Base);
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depthStencilRb->has_surface = screen->depthHasSurface;
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} else {
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/* depth renderbuffer */
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struct radeon_renderbuffer *depth =
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radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
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depth->has_surface = screen->depthHasSurface;
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}
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} else if (mesaVis->depthBits == 16) {
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/* just 16-bit depth buffer, no hw stencil */
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struct radeon_renderbuffer *depth =
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radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
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_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
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depth->has_surface = screen->depthHasSurface;
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}
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@ -64,8 +64,8 @@ radeon_renderbuffer_map(struct gl_context *ctx, struct gl_renderbuffer *rb)
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GL_MAP_READ_BIT | GL_MAP_WRITE_BIT,
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&map, &stride);
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rb->Map = map;
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rb->RowStrideBytes = stride;
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rrb->base.Map = map;
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rrb->base.RowStride = stride;
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}
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static void
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@ -77,8 +77,8 @@ radeon_renderbuffer_unmap(struct gl_context *ctx, struct gl_renderbuffer *rb)
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ctx->Driver.UnmapRenderbuffer(ctx, rb);
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rb->Map = NULL;
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rb->RowStrideBytes = 0;
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rrb->base.Map = NULL;
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rrb->base.RowStride = 0;
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}
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static void
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@ -334,7 +334,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
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atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
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if (rrb->cpp == 4)
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atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
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else switch (rrb->base.Format) {
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else switch (rrb->base.Base.Format) {
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case MESA_FORMAT_RGB565:
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atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
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break;
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@ -404,8 +404,8 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
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OUT_BATCH(0);
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OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
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if (rrb) {
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OUT_BATCH(((rrb->base.Width - 1) << RADEON_RE_WIDTH_SHIFT) |
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((rrb->base.Height - 1) << RADEON_RE_HEIGHT_SHIFT));
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OUT_BATCH(((rrb->base.Base.Width - 1) << RADEON_RE_WIDTH_SHIFT) |
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((rrb->base.Base.Height - 1) << RADEON_RE_HEIGHT_SHIFT));
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} else {
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OUT_BATCH(0);
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}
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@ -89,12 +89,12 @@ do_copy_texsubimage(struct gl_context *ctx,
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__FUNCTION__, face, level);
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fprintf(stderr, "to: x %d, y %d, offset %d\n", dstx, dsty, (uint32_t) dst_offset);
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fprintf(stderr, "from (%dx%d) width %d, height %d, offset %d, pitch %d\n",
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x, y, rrb->base.Width, rrb->base.Height, (uint32_t) src_offset, rrb->pitch/rrb->cpp);
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x, y, rrb->base.Base.Width, rrb->base.Base.Height, (uint32_t) src_offset, rrb->pitch/rrb->cpp);
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fprintf(stderr, "src size %d, dst size %d\n", rrb->bo->size, timg->mt->bo->size);
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}
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src_mesaformat = rrb->base.Format;
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src_mesaformat = rrb->base.Base.Format;
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dst_mesaformat = timg->base.Base.TexFormat;
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src_bpp = _mesa_get_format_bytes(src_mesaformat);
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dst_bpp = _mesa_get_format_bytes(dst_mesaformat);
|
||||
|
|
@ -126,7 +126,7 @@ do_copy_texsubimage(struct gl_context *ctx,
|
|||
|
||||
/* blit from src buffer to texture */
|
||||
return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp,
|
||||
rrb->base.Width, rrb->base.Height, x, y,
|
||||
rrb->base.Base.Width, rrb->base.Base.Height, x, y,
|
||||
timg->mt->bo, dst_offset, dst_mesaformat,
|
||||
timg->mt->levels[level].rowstride / dst_bpp,
|
||||
timg->base.Base.Width, timg->base.Base.Height,
|
||||
|
|
|
|||
|
|
@ -681,15 +681,16 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_form
|
|||
}
|
||||
|
||||
_mesa_init_teximage_fields(radeon->glCtx, texImage,
|
||||
rb->base.Width, rb->base.Height, 1, 0,
|
||||
rb->base.Base.Width, rb->base.Base.Height,
|
||||
1, 0,
|
||||
rb->cpp, texFormat);
|
||||
rImage->base.RowStride = rb->pitch / rb->cpp;
|
||||
|
||||
t->pp_txpitch &= (1 << 13) -1;
|
||||
pitch_val = rb->pitch;
|
||||
|
||||
t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
|
||||
| ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
|
||||
t->pp_txsize = ((rb->base.Base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
|
||||
| ((rb->base.Base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
|
||||
if (target == GL_TEXTURE_RECTANGLE_NV) {
|
||||
t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
|
||||
t->pp_txpitch = pitch_val;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue