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Add PCI IDs for the G33, Q33, and Q35 chipsets.

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This commit is contained in:
Wang Zhenyu 2007-06-05 11:42:43 -07:00 • committed by Eric Anholt
parent 08a2cc2d23
commit 8331d9d7aa
9 changed files with 47 additions and 8 deletions
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20
src/mesa/drivers/dri/i915/i915_texstate.c
View file

@ -491,13 +491,19 @@ static void i915SetTexImages( i915ContextPtr i915,
abort();
}
if (i915->intel.intelScreen->deviceID == PCI_CHIP_I945_G ||
i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GM ||
i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GME)
i945LayoutTextureImages( i915, tObj );
else
i915LayoutTextureImages( i915, tObj );
switch (i915->intel.intelScreen->deviceID) {
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
case PCI_CHIP_G33_G:
case PCI_CHIP_Q33_G:
case PCI_CHIP_Q35_G:
i945LayoutTextureImages( i915, tObj );
break;
default:
i915LayoutTextureImages( i915, tObj );
break;
}
t->Setup[I915_TEXREG_MS3] =
(((tObj->Image[0][t->intel.base.firstLevel]->Height - 1) << MS3_HEIGHT_SHIFT) |

6
src/mesa/drivers/dri/i915/intel_context.c
View file

@ -125,6 +125,12 @@ const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
chipset = "Intel(R) 945GM"; break;
case PCI_CHIP_I945_GME:
chipset = "Intel(R) 945GME"; break;
case PCI_CHIP_G33_G:
chipset = "Intel(R) G33"; break;
case PCI_CHIP_Q35_G:
chipset = "Intel(R) Q35"; break;
case PCI_CHIP_Q33_G:
chipset = "Intel(R) Q33"; break;
default:
chipset = "Unknown Intel Chipset"; break;
}

3
src/mesa/drivers/dri/i915/intel_context.h
View file

@ -455,6 +455,9 @@ extern int INTEL_DEBUG;
#define PCI_CHIP_I945_G 0x2772
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GME 0x27AE
#define PCI_CHIP_G33_G 0x29C2
#define PCI_CHIP_Q35_G 0x29B2
#define PCI_CHIP_Q33_G 0x29D2
/* ================================================================

3
src/mesa/drivers/dri/i915/intel_screen.c
View file

@ -515,6 +515,9 @@ static GLboolean intelCreateContext( const __GLcontextModes *mesaVis,
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
return i915CreateContext( mesaVis, driContextPriv,
sharedContextPrivate );

5
src/mesa/drivers/dri/i915/intel_tex.c
View file

@ -678,7 +678,10 @@ static void intelUploadTexImage( intelContextPtr intel,
*/
else if (intel->intelScreen->deviceID == PCI_CHIP_I945_G ||
intel->intelScreen->deviceID == PCI_CHIP_I945_GM ||
intel->intelScreen->deviceID == PCI_CHIP_I945_GME) {
intel->intelScreen->deviceID == PCI_CHIP_I945_GME ||
intel->intelScreen->deviceID == PCI_CHIP_G33_G ||
intel->intelScreen->deviceID == PCI_CHIP_Q33_G ||
intel->intelScreen->deviceID == PCI_CHIP_Q35_G) {
GLuint row_len = image->Width * image->TexFormat->TexelBytes;
GLubyte *dst = (GLubyte *)(t->BufAddr + offset);
GLubyte *src = (GLubyte *)image->Data;

9
src/mesa/drivers/dri/i915tex/intel_context.c
View file

@ -133,6 +133,15 @@ intelGetString(GLcontext * ctx, GLenum name)
case PCI_CHIP_I945_GME:
chipset = "Intel(R) 945GME";
break;
case PCI_CHIP_G33_G:
chipset = "Intel(R) G33";
break;
case PCI_CHIP_Q35_G:
chipset = "Intel(R) Q35";
break;
case PCI_CHIP_Q33_G:
chipset = "Intel(R) Q33";
break;
default:
chipset = "Unknown Intel Chipset";
break;

3
src/mesa/drivers/dri/i915tex/intel_context.h
View file

@ -386,6 +386,9 @@ extern int INTEL_DEBUG;
#define PCI_CHIP_I945_G 0x2772
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GME 0x27AE
#define PCI_CHIP_G33_G 0x29C2
#define PCI_CHIP_Q35_G 0x29B2
#define PCI_CHIP_Q33_G 0x29D2
/* ================================================================

3
src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c
View file

@ -80,6 +80,9 @@ intel_miptree_create(struct intel_context *intel,
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
case PCI_CHIP_G33_G:
case PCI_CHIP_Q33_G:
case PCI_CHIP_Q35_G:
ok = i945_miptree_layout(mt);
break;
case PCI_CHIP_I915_G:

3
src/mesa/drivers/dri/i915tex/intel_screen.c
View file

@ -753,6 +753,9 @@ intelCreateContext(const __GLcontextModes * mesaVis,
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
return i915CreateContext(mesaVis, driContextPriv, sharedContextPrivate);
default: