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ac: compute the DCC fast clear size per slice on GFX8

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-07-01 16:30:56 +02:00
parent 6517d226ac
commit 83297baf2d
2 changed files with 28 additions and 0 deletions
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27
src/amd/common/ac_surface.c
View file

@ -308,6 +308,33 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
* slice is the same size) it's easy to compute.
*/
surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
/* For arrays, we have to compute the DCC info again
* with one slice size to get a correct fast clear
* size.
*/
if (config->info.array_size > 1) {
AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
ret = AddrComputeDccInfo(addrlib,
AddrDccIn, AddrDccOut);
if (ret == ADDR_OK) {
/* If the DCC memory isn't properly
* aligned, the data are interleaved
* accross slices.
*/
if (AddrDccOut->dccRamSizeAligned)
surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
else
surf_level->dcc_slice_fast_clear_size = 0;
}
} else {
surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
}
}
}

1
src/amd/common/ac_surface.h
View file

@ -76,6 +76,7 @@ struct legacy_surf_level {
uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */
uint32_t dcc_offset; /* relative offset within DCC mip tree */
uint32_t dcc_fast_clear_size;
uint32_t dcc_slice_fast_clear_size;
unsigned nblk_x:15;
unsigned nblk_y:15;
enum radeon_surf_mode mode:2;