fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-29 08:00:12 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

nouveau: Skip cctl for atomic counters in tgsi

Browse source 
The tgsi path already marked all aliasing loads of atomic counters with
CACHE_CG, so we don't need to emit a cctl. This patch uses the cache
flag on the atomic to model whether the L1 cache needs the stale
values to be flushed or not.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14386>
This commit is contained in:
M Henning 2022-01-29 22:20:58 -05:00 • committed by Marge Bot
parent 850197b3e0
commit 8313a9231c
2 changed files with 8 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
View file

@ -2962,6 +2962,10 @@ Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
if (ind)
insn->setIndirect(0, 1, ind);
insn->subOp = subOp;
if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER &&
code->bufferAtomics[tgsi.getSrc(0).getIndex(0)])
insn->cache = nv50_ir::CACHE_CG;
}
for (int c = 0; c < 4; ++c)
if (dst0[c])

4
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
View file

@ -1708,6 +1708,10 @@ bool
NVC0LoweringPass::handleATOMCctl(Instruction *atom) {
// Flush L1 cache manually since atomics go directly to L2. This ensures
// that any later CA reads retrieve the updated data.
if (atom->cache != nv50_ir::CACHE_CA)
return false;
bld.setPosition(atom, true);
Instruction *cctl = bld.mkOp1(OP_CCTL, TYPE_NONE, NULL, atom->getSrc(0));