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i965: Eliminate brw->tcs.prog_data pointer.

Browse source 
Just say no to:

-   brw->tcs.base.prog_data = &brw->tcs.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_tcs_prog_data as needed.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
This commit is contained in:
Kenneth Graunke 2016-09-08 23:48:53 -07:00
parent 40258a13d5
commit 82c97ac710
8 changed files with 28 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -1100,7 +1100,6 @@ struct brw_context
struct {
struct brw_stage_state base;
struct brw_tcs_prog_data *prog_data;
/**
* True if the 3DSTATE_HS command most recently emitted to the 3D

1
src/mesa/drivers/dri/i965/brw_state_cache.c
View file

@ -399,7 +399,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
/* Also, NULL out any stale program pointers. */
brw->vs.base.prog_data = NULL;
brw->tcs.prog_data = NULL;
brw->tcs.base.prog_data = NULL;
brw->tes.prog_data = NULL;
brw->tes.base.prog_data = NULL;

1
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -686,7 +686,6 @@ brw_upload_tess_programs(struct brw_context *brw)
brw_upload_tcs_prog(brw);
brw_upload_tes_prog(brw);
} else {
brw->tcs.prog_data = NULL;
brw->tcs.base.prog_data = NULL;
brw->tes.prog_data = NULL;
brw->tes.base.prog_data = NULL;

10
src/mesa/drivers/dri/i965/brw_tcs.c
View file

@ -304,7 +304,7 @@ brw_codegen_tcs_prog(struct brw_context *brw,
key, sizeof(*key),
program, program_size,
&prog_data, sizeof(prog_data),
&stage_state->prog_offset, &brw->tcs.prog_data);
&stage_state->prog_offset, &brw->tcs.base.prog_data);
ralloc_free(mem_ctx);
if (!tcs)
ralloc_free(nir);
@ -378,13 +378,13 @@ brw_upload_tcs_prog(struct brw_context *brw)
if (!brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG,
&key, sizeof(key),
&stage_state->prog_offset, &brw->tcs.prog_data)) {
&stage_state->prog_offset,
&brw->tcs.base.prog_data)) {
bool success = brw_codegen_tcs_prog(brw, current[MESA_SHADER_TESS_CTRL],
tcp, &key);
assert(success);
(void)success;
}
brw->tcs.base.prog_data = &brw->tcs.prog_data->base.base;
}
@ -396,7 +396,7 @@ brw_tcs_precompile(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct brw_tcs_prog_key key;
uint32_t old_prog_offset = brw->tcs.base.prog_offset;
struct brw_tcs_prog_data *old_prog_data = brw->tcs.prog_data;
struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data;
bool success;
struct gl_tess_ctrl_program *tcp = (struct gl_tess_ctrl_program *)prog;
@ -430,7 +430,7 @@ brw_tcs_precompile(struct gl_context *ctx,
success = brw_codegen_tcs_prog(brw, shader_prog, btcp, &key);
brw->tcs.base.prog_offset = old_prog_offset;
brw->tcs.prog_data = old_prog_data;
brw->tcs.base.prog_data = old_prog_data;
return success;
}

8
src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
View file

@ -48,7 +48,7 @@ brw_upload_tcs_pull_constants(struct brw_context *brw)
return;
/* BRW_NEW_TCS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL);
/* _NEW_PROGRAM_CONSTANTS */
@ -80,7 +80,7 @@ brw_upload_tcs_ubo_surfaces(struct brw_context *brw)
return;
/* BRW_NEW_TCS_PROG_DATA */
struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_CTRL],
&brw->tcs.base, prog_data);
@ -108,7 +108,7 @@ brw_upload_tcs_abo_surfaces(struct brw_context *brw)
if (prog) {
/* BRW_NEW_TCS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_CTRL],
&brw->tcs.base, &brw->tcs.prog_data->base.base);
&brw->tcs.base, brw->tcs.base.prog_data);
}
}
@ -134,7 +134,7 @@ brw_upload_tcs_image_surfaces(struct brw_context *brw)
if (prog) {
/* BRW_NEW_TCS_PROG_DATA, BRW_NEW_IMAGE_UNITS */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_CTRL],
&brw->tcs.base, &brw->tcs.prog_data->base.base);
&brw->tcs.base, brw->tcs.base.prog_data);
}
}

14
src/mesa/drivers/dri/i965/gen7_hs_state.c
View file

@ -38,7 +38,7 @@ gen7_upload_tcs_push_constants(struct brw_context *brw)
if (active) {
/* BRW_NEW_TCS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL);
gen6_upload_push_constants(brw, &tcp->program.Base, prog_data,
@ -69,22 +69,24 @@ gen7_upload_hs_state(struct brw_context *brw)
/* BRW_NEW_TESS_PROGRAMS */
bool active = brw->tess_eval_program;
/* BRW_NEW_TCS_PROG_DATA */
const struct brw_vue_prog_data *prog_data = &brw->tcs.prog_data->base;
const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
const struct brw_tcs_prog_data *tcs_prog_data =
brw_tcs_prog_data(stage_state->prog_data);
if (active) {
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
GEN7_HS_SAMPLER_COUNT) |
SET_FIELD(prog_data->base.binding_table.size_bytes / 4,
SET_FIELD(prog_data->binding_table.size_bytes / 4,
GEN7_HS_BINDING_TABLE_ENTRY_COUNT) |
(devinfo->max_tcs_threads - 1));
OUT_BATCH(GEN7_HS_ENABLE |
GEN7_HS_STATISTICS_ENABLE |
SET_FIELD(brw->tcs.prog_data->instances - 1,
SET_FIELD(tcs_prog_data->instances - 1,
GEN7_HS_INSTANCE_COUNT));
OUT_BATCH(stage_state->prog_offset);
if (prog_data->base.total_scratch) {
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
ffs(stage_state->per_thread_scratch) - 11);
@ -92,7 +94,7 @@ gen7_upload_hs_state(struct brw_context *brw)
OUT_BATCH(0);
}
OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
SET_FIELD(prog_data->base.dispatch_grf_start_reg,
SET_FIELD(prog_data->dispatch_grf_start_reg,
GEN7_HS_DISPATCH_START_GRF));
/* Ignore URB semaphores */
OUT_BATCH(0);

4
src/mesa/drivers/dri/i965/gen7_urb.c
View file

@ -215,7 +215,9 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
unsigned gs_entry_size_bytes = gs_size * 64;
/* BRW_NEW_TCS_PROG_DATA */
unsigned hs_size = tess_present ? brw->tcs.prog_data->base.urb_entry_size : 1;
const struct brw_vue_prog_data *tcs_vue_prog_data =
brw_vue_prog_data(brw->tcs.base.prog_data);
unsigned hs_size = tess_present ? tcs_vue_prog_data->urb_entry_size : 1;
unsigned hs_entry_size_bytes = hs_size * 64;
/* BRW_NEW_TES_PROG_DATA */
unsigned ds_size = tess_present ? brw->tes.prog_data->base.urb_entry_size : 1;

14
src/mesa/drivers/dri/i965/gen8_hs_state.c
View file

@ -33,24 +33,26 @@ gen8_upload_hs_state(struct brw_context *brw)
const struct brw_stage_state *stage_state = &brw->tcs.base;
/* BRW_NEW_TESS_PROGRAMS */
bool active = brw->tess_eval_program;
/* BRW_NEW_HS_PROG_DATA */
const struct brw_vue_prog_data *prog_data = &brw->tcs.prog_data->base;
/* BRW_NEW_TCS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
const struct brw_tcs_prog_data *tcs_prog_data =
brw_tcs_prog_data(stage_state->prog_data);
if (active) {
BEGIN_BATCH(9);
OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
GEN7_HS_SAMPLER_COUNT) |
SET_FIELD(prog_data->base.binding_table.size_bytes / 4,
SET_FIELD(prog_data->binding_table.size_bytes / 4,
GEN7_HS_BINDING_TABLE_ENTRY_COUNT));
OUT_BATCH(GEN7_HS_ENABLE |
GEN7_HS_STATISTICS_ENABLE |
(devinfo->max_tcs_threads - 1) << GEN8_HS_MAX_THREADS_SHIFT |
SET_FIELD(brw->tcs.prog_data->instances - 1,
SET_FIELD(tcs_prog_data->instances - 1,
GEN7_HS_INSTANCE_COUNT));
OUT_BATCH(stage_state->prog_offset);
OUT_BATCH(0);
if (prog_data->base.total_scratch) {
if (prog_data->total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
ffs(stage_state->per_thread_scratch) - 11);
@ -59,7 +61,7 @@ gen8_upload_hs_state(struct brw_context *brw)
OUT_BATCH(0);
}
OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
SET_FIELD(prog_data->base.dispatch_grf_start_reg,
SET_FIELD(prog_data->dispatch_grf_start_reg,
GEN7_HS_DISPATCH_START_GRF));
OUT_BATCH(0); /* MBZ */
ADVANCE_BATCH();