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anv: move reg_mask push constant field to gfx

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This is used only for gfx stages as those are the only ones that can
promote UBOs to push constants.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33550>
This commit is contained in:
Lionel Landwerlin 2024-07-06 17:06:30 +03:00
parent 456d691310
commit 82b6a6f0b9
3 changed files with 11 additions and 10 deletions
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9
src/intel/vulkan/anv_nir_compute_push_layout.c
View file

@ -96,9 +96,10 @@ anv_nir_compute_push_layout(nir_shader *nir,
* the shader.
*/
const uint32_t push_reg_mask_start =
anv_drv_const_offset(push_reg_mask[nir->info.stage]);
const uint32_t push_reg_mask_end = push_reg_mask_start +
anv_drv_const_size(push_reg_mask[nir->info.stage]);
anv_drv_const_offset(gfx.push_reg_mask[nir->info.stage]);
const uint32_t push_reg_mask_end =
push_reg_mask_start +
anv_drv_const_size(gfx.push_reg_mask[nir->info.stage]);
push_start = MIN2(push_start, push_reg_mask_start);
push_end = MAX2(push_end, push_reg_mask_end);
}
@ -217,7 +218,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
if (robust_flags & BRW_ROBUSTNESS_UBO) {
const uint32_t push_reg_mask_offset =
anv_drv_const_offset(push_reg_mask[nir->info.stage]);
anv_drv_const_offset(gfx.push_reg_mask[nir->info.stage]);
assert(push_reg_mask_offset >= push_start);
prog_data->push_reg_mask_param =
(push_reg_mask_offset - push_start) / 4;

6
src/intel/vulkan/anv_private.h
View file

@ -3710,9 +3710,6 @@ struct anv_push_constants {
*/
uint32_t surfaces_base_offset;
/* Robust access pushed registers. */
uint64_t push_reg_mask[MESA_SHADER_STAGES];
/** Ray query globals (RT_DISPATCH_GLOBALS) */
uint64_t ray_query_globals;
@ -3723,6 +3720,9 @@ struct anv_push_constants {
/** Dynamic TCS input vertices */
uint32_t tcs_input_vertices;
/** Robust access pushed registers. */
uint64_t push_reg_mask[MESA_SHADER_STAGES];
} gfx;
struct {

6
src/intel/vulkan/genX_cmd_draw.c
View file

@ -449,7 +449,7 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
const struct anv_pipeline_bind_map *bind_map = &shader->bind_map;
struct anv_push_constants *push = &gfx_state->base.push_constants;
push->push_reg_mask[stage] = 0;
push->gfx.push_reg_mask[stage] = 0;
/* Start of the current range in the shader, relative to the start of
* push constants in the shader.
*/
@ -466,8 +466,8 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
MIN2(DIV_ROUND_UP(bound_size, 32) - range->start,
range->length);
assert(range_start_reg + bound_regs <= 64);
push->push_reg_mask[stage] |= BITFIELD64_RANGE(range_start_reg,
bound_regs);
push->gfx.push_reg_mask[stage] |=
BITFIELD64_RANGE(range_start_reg, bound_regs);
}
cmd_buffer->state.push_constants_dirty |=