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pvr: re-emit ppp state update when ds depth bits are set

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The driver needs to check for dynamic state depth writes and comparison flags,
as so to not miss re-emitting the ppp update from a dirty state.

Signed-off-by: Iliyan Dinev <iliyan.dinev@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
This commit is contained in:
Iliyan Dinev 2024-06-24 16:21:04 +01:00 • committed by Marge Bot
parent 1d46696887
commit 82a4c66635
1 changed files with 18 additions and 13 deletions
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31
src/imagination/vulkan/pvr_cmd_buffer.c
View file

@ -5870,6 +5870,21 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
return VK_SUCCESS;
}
static inline bool pvr_ppp_dynamic_state_isp_faces_and_control_dirty(
const BITSET_WORD *const dynamic_dirty)
{
return BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_RS_LINE_WIDTH) ||
BITSET_TEST(dynamic_dirty,
MESA_VK_DYNAMIC_RS_RASTERIZER_DISCARD_ENABLE);
}
static inline bool
pvr_ppp_state_update_required(const struct pvr_cmd_buffer *cmd_buffer)
{
@ -5895,12 +5910,8 @@ pvr_ppp_state_update_required(const struct pvr_cmd_buffer *cmd_buffer)
state->dirty.fragment_descriptors || state->dirty.vis_test ||
state->dirty.gfx_pipeline_binding || state->dirty.isp_userpass ||
state->push_consts[PVR_STAGE_ALLOCATION_FRAGMENT].dirty ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE) ||
pvr_ppp_dynamic_state_isp_faces_and_control_dirty(dynamic_dirty) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_FACTORS) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_RS_LINE_WIDTH) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_VP_SCISSORS) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_VP_SCISSOR_COUNT) ||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_VP_VIEWPORTS) ||
@ -5934,14 +5945,8 @@ pvr_emit_dirty_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
pvr_setup_output_select(cmd_buffer);
pvr_setup_isp_faces_and_control(cmd_buffer, &ispa);
pvr_setup_triangle_merging_flag(cmd_buffer, &ispa);
} else if (BITSET_TEST(dynamic_state->dirty,
MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK) ||
BITSET_TEST(dynamic_state->dirty,
MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE) ||
BITSET_TEST(dynamic_state->dirty,
MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK) ||
BITSET_TEST(dynamic_state->dirty,
MESA_VK_DYNAMIC_RS_LINE_WIDTH) ||
} else if (pvr_ppp_dynamic_state_isp_faces_and_control_dirty(
dynamic_state->dirty) ||
state->dirty.isp_userpass || state->dirty.vis_test) {
pvr_setup_isp_faces_and_control(cmd_buffer, NULL);
}